We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / intel / i82801dx / i82801dx.h

diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index d4e1aa09281970dd85f1e4f24c5826d5d57a1170..a38c793eda00520225b234cb94c91981cfb7f057 100644 (file)
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -1,19 +1,52 @@
-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. 
- * fb1 code is what we want, fb2 structure is needed however. 
- * so we need to get fb1 code for 82801dbm into fb2 structure. 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ * Copyright (C) 2004 Eric Biederman
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
+ * fb1 code is what we want, fb2 structure is needed however.
+ * so we need to get fb1 code for 82801dbm into fb2 structure.
  */
-/* What I did: took the 80801er stuff from fb2, verify it against the 
+/* What I did: took the 80801er stuff from fb2, verify it against the
  * db stuff in fb1, and made sure it was right.
  */
 
 #ifndef I82801DX_H
 #define I82801DX_H
 
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801dx_enable(device_t dev);
 #endif
 
+/*
+ * HPET Memory Address Range. Possible values:
+ * 0xfed00000 for FED0_0000h - FED0_03FFh
+ * 0xfed01000 for FED0_1000h - FED0_13FFh
+ * 0xfed02000 for FED0_2000h - FED0_23FFh
+ * 0xfed03000 for FED0_3000h - FED0_33FFh
+ */
+#define HPET_ADDR              0xfed00000
+
+#define DEBUG_PERIODIC_SMIS 0
+
 #define MAINBOARD_POWER_OFF    0
 #define MAINBOARD_POWER_ON     1
 #define MAINBOARD_POWER_KEEP   2
@@ -23,15 +56,23 @@ extern void i82801dx_enable(device_t dev);
 #endif
 
 /*
-000 = Non-combined. P0 is primary master. P1 is secondary master.
-001 = Non-combined. P0 is secondary master. P1 is primary master.
-100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
-disabled.
-101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
-110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
-channel disabled.
-111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
-*/
+ * 000 = Non-combined. P0 is primary master. P1 is secondary master.
+ * 001 = Non-combined. P0 is secondary master. P1 is primary master.
+ * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
+ *       Primary IDE channel disabled.
+ * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
+ * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
+ *       slave; Secondary IDE channel disabled.
+ * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
+ */
+/* PCI Configuration Space (D31:F1) */
+#define IDE_TIM_PRI            0x40    /* IDE timings, primary */
+#define IDE_TIM_SEC            0x42    /* IDE timings, secondary */
+
+/* IDE_TIM bits */
+#define IDE_DECODE_ENABLE      (1 << 15)
+
+
 
 #define PCI_DMA_CFG     0x90
 #define SERIRQ_CNTL     0x64
@@ -43,12 +84,20 @@ channel disabled.
 #define PCICMD          0x04
 #define PMBASE          0x40
 #define   PMBASE_ADDR  0x0400
+#define   DEFAULT_PMBASE PMBASE_ADDR
 #define ACPI_CNTL       0x44
 #define BIOS_CNTL       0x4E
 #define GPIO_BASE       0x58
 #define GPIO_CNTL       0x5C
-#define PIRQA_ROUT      0x60
-#define PIRQE_ROUT      0x68
+#define   GPIOBASE_ADDR 0x0500
+#define PIRQA_ROUT     0x60
+#define PIRQB_ROUT     0x61
+#define PIRQC_ROUT     0x62
+#define PIRQD_ROUT     0x63
+#define PIRQE_ROUT     0x68
+#define PIRQF_ROUT     0x69
+#define PIRQG_ROUT     0x6A
+#define PIRQH_ROUT     0x6B
 #define COM_DEC         0xE0
 #define LPC_EN          0xE6
 #define FUNC_DIS        0xF2
@@ -82,9 +131,9 @@ channel disabled.
 #define SMBTRNSADD 0x9
 #define SMBSLVDATA 0xa
 #define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf 
+#define SMBUS_PIN_CTL  0xf
 
-/* Between 1-10 seconds, We should never timeout normally 
+/* Between 1-10 seconds, We should never timeout normally
  * Longer than this is just painful when a timeout condition occurs.
  */
 #define SMBUS_TIMEOUT (100*1000)
@@ -160,4 +209,13 @@ channel disabled.
 #define TCOBASE                0x60 /* TCO Base Address Register */
 #define TCO1_CNT       0x08 /* TCO1 Control Register */
 
+#define GEN_PMCON_1            0xa0
+#define GEN_PMCON_2            0xa2
+#define GEN_PMCON_3            0xa4
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD       (1 << 2)
+#define RTC_POWER_FAILED       (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
 #endif /* I82801DX_H */