We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / intel / i82371eb / i82371eb_isa.c

diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
index a521d86bb0cf7d4cc4272122c2a3d8d40072a5c5..0cc46a618c6e1efa0d7d1b629b356cc80a1be5dd 100644 (file)
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -25,24 +25,16 @@
 #include <device/pci_ids.h>
 #include <pc80/isa-dma.h>
 #include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
 #include "i82371eb.h"
 
 static void isa_init(struct device *dev)
 {
-       u16 reg16;
        u32 reg32;
 
        /* Initialize the real time clock (RTC). */
        rtc_init(0);
 
-       /* Enable access to all BIOS regions. */
-       reg16 = pci_read_config16(dev, XBCS);
-       reg16 |= LOWER_BIOS_ENABLE;
-       reg16 |= EXT_BIOS_ENABLE;
-       reg16 |= EXT_BIOS_ENABLE_1MB;
-       reg16 &= ~(WRITE_PROTECT_ENABLE);       /* Disable ROM write access. */
-       pci_write_config16(dev, XBCS, reg16);
-
        /*
         * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
         * bus, which is a subset of ISA. We select the full ISA bus here.
@@ -73,12 +65,12 @@ static void sb_read_resources(struct device *dev)
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-const struct device_operations isa_ops = {
+static const struct device_operations isa_ops = {
        .read_resources         = sb_read_resources,
        .set_resources          = pci_dev_set_resources,
        .enable_resources       = pci_dev_enable_resources,