#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i3100.h"
#define ACPI_BAR 0x40
#define GPIO_BAR 0x48
#define RCBA 0xf0
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xA0
+#define GEN_PMCON_2 0xA2
+#define GEN_PMCON_3 0xA4
+
#define NMI_OFF 0
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- u32 value_low, value_high;
- u32 ioapic_base = 0xfec00000;
- volatile u32 *l;
- u32 interrupts;
- struct resource *res;
-
- /* Enable IO APIC */
- res = find_resource(dev, RCBA);
- if (!res) {
- return;
- }
- *((u8 *)(res->base + 0x31ff)) |= (1 << 0);
-
- l = (u32 *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%d IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-
- /* Put the APIC in virtual wire mode */
- l[0] = 0x10;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
-#define SERIRQ_CNTL 0x64
static void i3100_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
}
}
+static void i3100_power_options(device_t dev) {
+ u8 reg8;
+ u16 reg16;
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int nmi_option;
+
+ /* Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ */
+ get_option(&pwr_on, "power_on_after_fail");
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ reg8 &= 0xfe;
+ if (pwr_on) {
+ reg8 &= ~1;
+ } else {
+ reg8 |= 1;
+ }
+ /* avoid #S4 assertions */
+ reg8 |= (3 << 4);
+ /* minimum asssertion is 1 to 2 RTCCLK */
+ reg8 &= ~(1 << 3);
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ /* Higher Nibble must be 0 */
+ reg8 &= 0x0f;
+ /* IOCHK# NMI Enable */
+ reg8 &= ~(1 << 3);
+ /* PCI SERR# Enable */
+ // reg8 &= ~(1 << 2);
+ /* PCI SERR# Disable for now */
+ reg8 |= (1 << 2);
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ /* Set NMI. */
+ printk(BIOS_INFO, "NMI sources enabled.\n");
+ reg8 &= ~(1 << 7);
+ } else {
+ /* Can't mask NMI from PCI-E and NMI_NOW */
+ printk(BIOS_INFO, "NMI sources disabled.\n");
+ reg8 |= ( 1 << 7);
+ }
+ outb(reg8, 0x70);
+
+ // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~((3 << 0) | (1 << 10));
+ reg16 |= (1 << 3) | (1 << 5);
+ /* CLKRUN_EN */
+ // reg16 |= (1 << 2);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ // Set the board's GPI routing.
+ // i82801gx_gpi_routing(dev);
+}
static void i3100_gpio_init(device_t dev)
{
static void lpc_init(struct device *dev)
{
- u8 byte;
- int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
+ struct resource *res;
- setup_ioapic(dev);
+ /* Enable IO APIC */
+ res = find_resource(dev, RCBA);
+ if (!res) {
+ return;
+ }
+ *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0);
+
+ // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
+ // (register 0x10/0x11) while the old code used int 1 (register 0x12)
+ // ... Why?
+ setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
pci_write_config32(dev, 0xd0, 0x00000000);
i3100_enable_serial_irqs(dev);
- get_option(&pwr_on, "power_on_after_fail");
- byte = pci_read_config8(dev, 0xa4);
- byte &= 0xfe;
- if (!pwr_on) {
- byte |= 1;
- }
- pci_write_config8(dev, 0xa4, byte);
- printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
-
/* Set up the PIRQ */
i3100_pirq_init(dev);
+ /* Setup power options */
+ i3100_power_options(dev);
+
/* Set the state of the gpio lines */
i3100_gpio_init(dev);
/* Add the GPIO BAR */
res = pci_get_resource(dev, GPIO_BAR);
- /* Add an extra subtractive resource for both memory and I/O */
+ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add resource for RCBA */
res = new_resource(dev, RCBA);
/* Enable the RCBA */
pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
-
- enable_childrens_resources(dev);
}
static struct pci_operations lops_pci = {
.ops_pci = &lops_pci,
};
-static struct pci_driver lpc_driver __pci_driver = {
+static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_3100_LPC,
};
-static struct pci_driver lpc_driver_ep80579 __pci_driver = {
+static const struct pci_driver lpc_driver_ep80579 __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_EP80579_LPC,
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