We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / intel / esb6300 / esb6300_pic.c

diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c
index 97635ae524ae8ef84c059608dbc73a161f744387..b9bfdf1fe3d1c325b4a9d893d2f10009ef47652b 100644 (file)
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/esb6300_pic.c
@@ -6,50 +6,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <arch/ioapic.h>
 #include "esb6300.h"
 
-#define ALL            (0xff << 24)
-#define NONE           (0)
-#define DISABLED       (1 << 16)
-#define ENABLED                (0 << 16)
-#define TRIGGER_EDGE   (0 << 15)
-#define TRIGGER_LEVEL  (1 << 15)
-#define POLARITY_HIGH  (0 << 13)
-#define POLARITY_LOW   (1 << 13)
-#define PHYSICAL_DEST  (0 << 11)
-#define LOGICAL_DEST   (1 << 11)
-#define ExtINT         (7 << 8)
-#define NMI            (4 << 8)
-#define SMI            (2 << 8)
-#define INT            (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
-       int i;
-       unsigned long value_low, value_high;
-       unsigned long ioapic_base = 0xfec10000;
-       volatile unsigned long *l;
-       unsigned interrupts;
-
-       l = (unsigned long *) ioapic_base;
-
-       l[0] = 0x01;
-       interrupts = (l[04] >> 16) & 0xff;
-       for (i = 0; i < interrupts; i++) {
-               l[0] = (i * 2) + 0x10;
-               l[4] = DISABLED;
-               value_low = l[4];
-               l[0] = (i * 2) + 0x11;
-               l[4] = NONE; /* Should this be an address? */
-               value_high = l[4];
-               if (value_low == 0xffffffff) {
-                       printk_warning("%s IO APIC not responding.\n", 
-                               dev_path(dev));
-                       return;
-               }
-       }
-}
-
 static void pic_init(struct device *dev)
 {
 
@@ -64,7 +23,7 @@ static void pic_init(struct device *dev)
        pci_write_config8(dev, 0x3c, 0xff);
 
        /* Setup the ioapic */
-       setup_ioapic(dev);
+       clear_ioapic(IO_APIC_ADDR + 0x10000);
 }
 
 static void pic_read_resources(device_t dev)
@@ -76,12 +35,12 @@ static void pic_read_resources(device_t dev)
 
        /* Report the pic1 mbar resource */
        res = new_resource(dev, 0x44);
-       res->base  = 0xfec10000;
+       res->base  = IO_APIC_ADDR + 0x10000;
        res->size  = 256;
        res->limit = res->base + res->size -1;
        res->align = 8;
        res->gran  = 8;
-       res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | 
+       res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
                IORESOURCE_STORED | IORESOURCE_ASSIGNED;
        dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 }