#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "esb6300.h"
#define ACPI_BAR 0x40
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%d IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-
- /* Put the ioapic in virtual wire mode */
- l[0] = 0 + 0x10;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
#define SERIRQ_CNTL 0x64
static void esb6300_enable_serial_irqs(device_t dev)
{
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_use_sel, gpio_use_sel2;
- int i;
// gpio_use_sel = 0x1B003100;
// gpio_use_sel2 = 0x03000000;
gpio_use_sel = 0x1BBC31C0;
gpio_use_sel2 = 0x03000FE1;
#if 0
+ int i;
for(i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ESB6300_GPIO_USE_MASK) {
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_io_sel, gpio_io_sel2;
- int i;
// gpio_io_sel = 0x0000ffff;
// gpio_io_sel2 = 0x00000000;
gpio_io_sel = 0x1900ffff;
gpio_io_sel2 = 0x00000fe1;
#if 0
+ int i;
for(i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
case ESB6300_GPIO_SEL_OUTPUT: val = 0; break;
case ESB6300_GPIO_SEL_INPUT: val = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
{
uint32_t gpio_lvl, gpio_lvl2;
uint32_t gpio_blink;
- int i;
// gpio_lvl = 0x1b3f0000;
// gpio_blink = 0x00040000;
gpio_blink = 0x00000000;
gpio_lvl2 = 0x00000fff;
#if 0
+ int i;
for(i = 0; i < 64; i++) {
int val, blink;
switch(config->gpio[i] & ESB6300_GPIO_LVL_MASK) {
case ESB6300_GPIO_LVL_LOW: val = 0; blink = 0; break;
case ESB6300_GPIO_LVL_HIGH: val = 1; blink = 0; break;
case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_inv;
- int i;
gpio_inv = 0x00003100;
#if 0
+ int i;
for(i = 0; i < 32; i++) {
int val;
switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {
case ESB6300_GPIO_INV_OFF: val = 0; break;
case ESB6300_GPIO_INV_ON: val = 1; break;
- default:
+ default:
continue;
}
gpio_inv &= ~( 1 << i);
/* Find the GPIO bar */
res = find_resource(dev, GPIO_BAR);
if (!res) {
- return;
+ return;
}
/* Set the use selects */
{
uint8_t byte;
uint32_t value;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
+ int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* sata settings */
pci_write_config32(dev, 0x58, 0x00001181);
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(dev);
+ setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
pci_write_config8(dev, 0xa0, 0x20);
pci_write_config8(dev, 0xad, 0x03);
pci_write_config8(dev, 0xbb, 0x09);
-
+
esb6300_enable_serial_irqs(dev);
esb6300_pci_dma_cfg(dev);
byte |= 1;
}
pci_write_config8(dev, 0xa4, byte);
- printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+ printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */
esb6300_pirq_init(dev);
-
+
/* Set the state of the gpio lines */
esb6300_gpio_init(dev);
/* Add the GPIO BAR */
res = pci_get_resource(dev, GPIO_BAR);
- /* Add an extra subtractive resource for both memory and I/O */
+ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void esb6300_lpc_enable_resources(device_t dev)
acpi_cntl = pci_read_config8(dev, 0x44);
acpi_cntl |= (1 << 4);
pci_write_config8(dev, 0x44, acpi_cntl);
-
+
/* Enable the GPIO bar */
gpio_cntl = pci_read_config8(dev, 0x5c);
gpio_cntl |= (1 << 4);
pci_write_config8(dev, 0x5c, gpio_cntl);
-
- enable_childrens_resources(dev);
}
static struct pci_operations lops_pci = {
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