We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / sb700 / sb700_sm.c

diff --git a/src/southbridge/amd/sb700/sb700_sm.c b/src/southbridge/amd/sb700/sb700_sm.c
index d053aff0fd3be9e7d52127e147bd420f158afe43..e700c0b5f360d2d72831742b4ef9917692f5278e 100644 (file)
--- a/src/southbridge/amd/sb700/sb700_sm.c
+++ b/src/southbridge/amd/sb700/sb700_sm.c
@@ -72,7 +72,6 @@ static void sm_init(device_t dev)
        dword |= 1 << 13;
        pci_write_config16(dev, 0x64, dword);
 
-
        /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
        /* rpr 2.1 Enabling Legacy Interrupt */
        dword = pci_read_config8(dev, 0x62);
@@ -207,7 +206,7 @@ static void sm_init(device_t dev)
        /* 4.14:Enabling Requester ID for upstream traffic. */
        abcfg_reg(0x98, 1 << 16, 1 << 16);
 
-       /* 9.2: Enableing IDE Data Bus DD7 Pull Down Resistor */
+       /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
        byte = pm2_ioread(0xE5);
        byte |= 1 << 2;
        pm2_iowrite(0xE5, byte);
@@ -282,6 +281,7 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
 
        return do_smbus_write_byte(res->base, device, address, val);
 }
+
 static struct smbus_bus_operations lops_smbus_bus = {
        .recv_byte = lsmbus_recv_byte,
        .send_byte = lsmbus_send_byte,
@@ -308,7 +308,7 @@ static void sb700_sm_read_resources(device_t dev)
 
        /* apic */
        res = new_resource(dev, 0x74);
-       res->base  = 0xfec00000;
+       res->base  = IO_APIC_ADDR;
        res->size = 256 * 0x10;
        res->limit = 0xFFFFFFFFUL;      /* res->base + res->size -1; */
        res->align = 8;
@@ -335,10 +335,9 @@ static void sb700_sm_read_resources(device_t dev)
        res->gran = 8;
        res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
 
-
        compact_resources(dev);
-
 }
+
 static void sb700_sm_set_resources(struct device *dev)
 {
        struct resource *res;
@@ -346,8 +345,7 @@ static void sb700_sm_set_resources(struct device *dev)
 
        pci_dev_set_resources(dev);
 
-
-       /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
+       /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
        byte = pm_ioread(0x52);
        byte |= 1 << 6;
        pm_iowrite(0x52, byte);
@@ -365,6 +363,7 @@ static void sb700_sm_set_resources(struct device *dev)
 static struct pci_operations lops_pci = {
        .set_subsystem = pci_dev_set_subsystem,
 };
+
 static struct device_operations smbus_ops = {
        .read_resources = sb700_sm_read_resources,
        .set_resources = sb700_sm_set_resources,
@@ -374,6 +373,7 @@ static struct device_operations smbus_ops = {
        .ops_pci = &lops_pci,
        .ops_smbus_bus = &lops_smbus_bus,
 };
+
 static const struct pci_driver smbus_driver __pci_driver = {
        .ops = &smbus_ops,
        .vendor = PCI_VENDOR_ID_ATI,