We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / cs5536 / cs5536.c

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 43f3b1290e9a1331f49500882e00c8a02f0d7a01..a2ac44647f4b61c2578b7baabe39fae64755c64e 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
@@ -247,7 +248,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
 
        isa_dma_init();
 }
-                       
+
 
 /**
  * Depending on settings in the config struct, enable COM1 or COM2 or both.
@@ -263,8 +264,8 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
        u16 addr = 0;
        u32 gpio_addr;
        device_t dev;
-       
-       dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+
+       dev = dev_find_device(PCI_VENDOR_ID_AMD,
                        PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
        gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
        gpio_addr &= ~1;        /* Clear I/O bit */
@@ -431,7 +432,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
        msr_t msr;
        device_t dev;
 
-       dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+       dev = dev_find_device(PCI_VENDOR_ID_AMD,
                        PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
        if (dev) {
 
@@ -452,7 +453,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
                write32(bar + HCCPARAMS, 0x00005012);
        }
 
-       dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+       dev = dev_find_device(PCI_VENDOR_ID_AMD,
                        PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
        if (dev) {
                bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -480,7 +481,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
         * - set PADEN (former OTGPADEN) bit in uoc register
         * - set APU bit in uoc register */
        if (sb->enable_USBP4_device) {
-               dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+               dev = dev_find_device(PCI_VENDOR_ID_AMD,
                                PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
                if (dev) {
                        bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -499,13 +500,13 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
        }
 
        /* Disable virtual PCI UDC and OTG headers */
-       dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+       dev = dev_find_device(PCI_VENDOR_ID_AMD,
                        PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
        if (dev) {
                pci_write_config32(dev, 0x7C, 0xDEADBEEF);
        }
 
-       dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+       dev = dev_find_device(PCI_VENDOR_ID_AMD,
                        PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
        if (dev) {
                pci_write_config32(dev, 0x7C, 0xDEADBEEF);
@@ -513,14 +514,11 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 }
 
 /****************************************************************************
- * 
- *     ChipsetInit 
+ *
+ *     ChipsetInit
  *
  *     Called from northbridge init (Pre-VSA).
  *
- *     NOTE! This function is NOT called if the CS5536 is combined with
- *     an AMD Geode GX2. It's ONLY used on Geode LX based systems.
- * 
  ****************************************************************************/
 void chipsetinit(void)
 {
@@ -530,8 +528,7 @@ void chipsetinit(void)
        struct southbridge_amd_cs5536_config *sb;
        struct msrinit *csi;
 
-       dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-                       PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+       dev = dev_find_slot(0, PCI_DEVFN(0xf, 0));
 
        if (!dev) {
                printk(BIOS_ERR, "CS5536 not found.\n");
@@ -655,13 +652,12 @@ static void cs5536_read_resources(device_t dev)
 
        res = new_resource(dev, 1);
        res->base = 0x0UL;
-       res->size = 0x400UL;
+       res->size = 0x1000UL;
        res->limit = 0xffffUL;
-       res->flags = IORESOURCE_IO |
-                    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+       res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
@@ -672,17 +668,10 @@ static void southbridge_enable(struct device *dev)
 
 }
 
-static void cs5536_pci_dev_enable_resources(device_t dev)
-{
-       printk(BIOS_ERR, "cs5536: %s()\n", __func__);
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static struct device_operations southbridge_ops = {
        .read_resources = cs5536_read_resources,
        .set_resources = pci_dev_set_resources,
-       .enable_resources = cs5536_pci_dev_enable_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init = southbridge_init,
 //      .enable                   = southbridge_enable,
        .scan_bus = scan_static_bus,