We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / cs5536 / cs5536.c

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 29747db215b5ebdac33e6de51d70bcc61afc1604..a2ac44647f4b61c2578b7baabe39fae64755c64e 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
@@ -651,13 +652,12 @@ static void cs5536_read_resources(device_t dev)
 
        res = new_resource(dev, 1);
        res->base = 0x0UL;
-       res->size = 0x400UL;
+       res->size = 0x1000UL;
        res->limit = 0xffffUL;
-       res->flags = IORESOURCE_IO |
-                    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+       res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
@@ -668,17 +668,10 @@ static void southbridge_enable(struct device *dev)
 
 }
 
-static void cs5536_pci_dev_enable_resources(device_t dev)
-{
-       printk(BIOS_ERR, "cs5536: %s()\n", __func__);
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static struct device_operations southbridge_ops = {
        .read_resources = cs5536_read_resources,
        .set_resources = pci_dev_set_resources,
-       .enable_resources = cs5536_pci_dev_enable_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init = southbridge_init,
 //      .enable                   = southbridge_enable,
        .scan_bus = scan_static_bus,