The GPIOs used for UART2 RX and TX were reversed.

[coreboot.git] / src / southbridge / amd / cs5536 / cs5536.c

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index ef5064a8a8a8ed29bfa7fec0847d55ca465b3ac1..9f4e90ed01d1bfe28b6a9b5c1caa836036f7b205 100644 (file)
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -356,19 +356,19 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
                msr.lo |= sb->com2_irq << 28;
                wrmsr(MDD_IRQM_YHIGH, msr);
 
-               /* GPIO3 - UART2_RX */
-               /* Set: Output Enable  (0x4) */
-               outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+               /* GPIO4 - UART2_RX */
+               /* Set: Output Enable (0x4) */
+               outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
                /* Set: OUTAUX1 Select (0x10) */
-               outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+               outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
 
-               /* GPIO4 - UART2_TX */
-               /* Set: Input Enable   (0x20) */
-               outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
-               /* Set: INAUX1 Select  (0x34) */
-               outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+               /* GPIO3 - UART2_TX */
+               /* Set: Input Enable (0x20) */
+               outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+               /* Set: INAUX1 Select (0x34) */
+               outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
 
-               /* Set: GPIO 3 + 3 Pull Up         (0x18) */
+               /* Set: GPIO 3 and 4 Pull Up (0x18) */
                outl(GPIOL_3_SET | GPIOL_4_SET,
                     gpio_addr + GPIOL_PULLUP_ENABLE);