We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / cs5535 / cs5535.c

diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 50b62df0c3dd43a1f0da56c917d443be63810060..42707c049c7ecda5fb89e82ffce5ff6f70ab9bcd 100644 (file)
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -1,5 +1,6 @@
 
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
@@ -71,33 +72,26 @@ static void southbridge_enable(struct device *dev)
 
 static void cs5535_read_resources(device_t dev)
 {
-       struct resource* res;
+       struct resource *res;
 
        pci_dev_read_resources(dev);
 
        res = new_resource(dev, 1);
        res->base = 0x0UL;
-       res->size = 0x400UL;
+       res->size = 0x1000UL;
        res->limit = 0xffffUL;
        res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void cs5535_pci_dev_enable_resources(device_t dev)
-{
-       printk(BIOS_SPEW, "cs5535.c: %s()\n", __func__);
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static struct device_operations southbridge_ops = {
        .read_resources   = cs5535_read_resources,
        .set_resources    = pci_dev_set_resources,
-       .enable_resources = cs5535_pci_dev_enable_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init             = southbridge_init,
        .enable           = southbridge_enable,
        .scan_bus         = scan_static_bus,