We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / cs5535 / cs5535.c

diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 17bd902e0ba3b3d5320308d35bac1bb980ebe703..42707c049c7ecda5fb89e82ffce5ff6f70ab9bcd 100644 (file)
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -1,5 +1,6 @@
 
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
@@ -21,7 +22,7 @@ static void nvram_on(struct device *dev)
        /* Set positive decode on ROM */
        /* Also, there is no apparent reason to turn off the devoce on the */
        /* IDE devices */
-       
+
        reg = pci_read_config8(dev, 0x5b);
        reg |= 1 << 5;  /* ROM Decode */
        reg |= 1 << 3;  /* Primary IDE decode */
@@ -39,14 +40,14 @@ static void nvram_on(struct device *dev)
 
        *flash = 0xf0;
 
-       printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
+       printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
 #endif
 }
 
-       
+
 static void southbridge_init(struct device *dev)
 {
-       printk_spew("cs5535: %s\n", __func__);
+       printk(BIOS_SPEW, "cs5535: %s\n", __func__);
        nvram_on(dev);
 }
 
@@ -56,48 +57,41 @@ static void dump_south(struct device *dev)
        int i, j;
 
        for(i=0; i<256; i+=16) {
-               printk_debug("0x%02x: ", i);
+               printk(BIOS_DEBUG, "0x%02x: ", i);
                for(j=0; j<16; j++)
-                       printk_debug("%02x ", pci_read_config8(dev, i+j));
-               printk_debug("\n");
+                       printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
+               printk(BIOS_DEBUG, "\n");
        }
 }
 */
 
 static void southbridge_enable(struct device *dev)
 {
-       printk_spew("%s: dev is %p\n", __func__, dev);
+       printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
 }
 
 static void cs5535_read_resources(device_t dev)
 {
-       struct resource* res;
+       struct resource *res;
 
        pci_dev_read_resources(dev);
 
        res = new_resource(dev, 1);
        res->base = 0x0UL;
-       res->size = 0x400UL;
+       res->size = 0x1000UL;
        res->limit = 0xffffUL;
        res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void cs5535_pci_dev_enable_resources(device_t dev)
-{
-       printk_spew("cs5535.c: %s()\n", __func__);
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static struct device_operations southbridge_ops = {
        .read_resources   = cs5535_read_resources,
        .set_resources    = pci_dev_set_resources,
-       .enable_resources = cs5535_pci_dev_enable_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init             = southbridge_init,
        .enable           = southbridge_enable,
        .scan_bus         = scan_static_bus,