We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / amd8111 / amd8111_lpc.c

diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index edb32c240c8c830f23da4ce2ab6446cfbc51322c..e9bd5fc42b22940b8ce6404123d6215d52b8ba8a 100644 (file)
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -19,11 +19,11 @@
 static void enable_hpet(struct device *dev)
 {
        unsigned long hpet_address;
-       
+
        pci_write_config32(dev,0xa0, 0xfed00001);
        hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
-       printk_debug("enabling HPET @0x%lx\n", hpet_address);
-       
+       printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
+
 }
 
 static void lpc_init(struct device *dev)
@@ -40,7 +40,7 @@ static void lpc_init(struct device *dev)
 
        /* posted memory write enable */
        byte = pci_read_config8(dev, 0x46);
-       pci_write_config8(dev, 0x46, byte | (1<<0)); 
+       pci_write_config8(dev, 0x46, byte | (1<<0));
 
        /* Enable 5Mib Rom window */
        byte = pci_read_config8(dev, 0x43);
@@ -65,11 +65,11 @@ static void lpc_init(struct device *dev)
        pci_write_config8(dev, 0x40, byte);
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
-       if (nmi_option) {                       
+       if (nmi_option) {
                byte |= (1 << 7); /* set NMI */
                pci_write_config8(dev, 0x40, byte);
        }
-       
+
        /* Initialize the real time clock */
        rtc_init(0);
 
@@ -101,20 +101,14 @@ static void amd8111_lpc_read_resources(device_t dev)
                     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void amd8111_lpc_enable_resources(device_t dev)
-{
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-       pci_write_config32(dev, 0x70, 
+       pci_write_config32(dev, 0x70,
                           ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -125,7 +119,7 @@ static struct pci_operations lops_pci = {
 static struct device_operations lpc_ops  = {
        .read_resources   = amd8111_lpc_read_resources,
        .set_resources    = pci_dev_set_resources,
-       .enable_resources = amd8111_lpc_enable_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init             = lpc_init,
        .scan_bus         = scan_static_bus,
        .enable           = amd8111_enable,