We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / amd / amd8111 / amd8111_lpc.c

diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index c239f7e7cf26f6ec7826c263b6e71232e3e0f56d..e9bd5fc42b22940b8ce6404123d6215d52b8ba8a 100644 (file)
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -10,99 +10,20 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
 #include <stdlib.h>
 #include "amd8111.h"
 
 #define NMI_OFF 0
 
-struct ioapicreg {
-       unsigned int reg;
-       unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL            (0xff << 24)
-#define NONE           (0)
-#define DISABLED       (1 << 16)
-#define ENABLED                (0 << 16)
-#define TRIGGER_EDGE   (0 << 15)
-#define TRIGGER_LEVEL  (1 << 15)
-#define POLARITY_HIGH  (0 << 13)
-#define POLARITY_LOW   (1 << 13)
-#define PHYSICAL_DEST  (0 << 11)
-#define LOGICAL_DEST   (1 << 11)
-#define ExtINT         (7 << 8)
-#define NMI            (4 << 8)
-#define SMI            (2 << 8)
-#define INT            (1 << 8)
-       /* IO-APIC virtual wire mode configuration */
-       /* mask, trigger, polarity, destination, delivery, vector */
-       {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
-       {   1, DISABLED, NONE},
-       {   2, DISABLED, NONE},
-       {   3, DISABLED, NONE},
-       {   4, DISABLED, NONE},
-       {   5, DISABLED, NONE},
-       {   6, DISABLED, NONE},
-       {   7, DISABLED, NONE},
-       {   8, DISABLED, NONE},
-       {   9, DISABLED, NONE},
-       {  10, DISABLED, NONE},
-       {  11, DISABLED, NONE},
-       {  12, DISABLED, NONE},
-       {  13, DISABLED, NONE},
-       {  14, DISABLED, NONE},
-       {  15, DISABLED, NONE},
-       {  16, DISABLED, NONE},
-       {  17, DISABLED, NONE},
-       {  18, DISABLED, NONE},
-       {  19, DISABLED, NONE},
-       {  20, DISABLED, NONE},
-       {  21, DISABLED, NONE},
-       {  22, DISABLED, NONE},
-       {  23, DISABLED, NONE},
-       /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(void)
-{
-       int i;
-       unsigned long value_low, value_high;
-       unsigned long ioapic_base = 0xfec00000;
-       volatile unsigned long *l;
-       struct ioapicreg *a = ioapicregvalues;
-       unsigned long bsp_apicid = lapicid();
-
-       l = (unsigned long *) ioapic_base;
-
-       ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
-       printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); 
-       
-       for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
-            i++, a++) {
-               l[0] = (a->reg * 2) + 0x10;
-               l[4] = a->value_low;
-               value_low = l[4];
-               l[0] = (a->reg *2) + 0x11;
-               l[4] = a->value_high;
-               value_high = l[4];
-               if ((i==0) && (value_low == 0xffffffff)) {
-                       printk_warning("IO APIC not responding.\n");
-                       return;
-               }
-               printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", 
-                           a->reg, a->value_low, a->value_high);
-       }
-}
-
 static void enable_hpet(struct device *dev)
 {
        unsigned long hpet_address;
-       
+
        pci_write_config32(dev,0xa0, 0xfed00001);
        hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
-       printk_debug("enabling HPET @0x%x\n", hpet_address);
-       
+       printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
+
 }
 
 static void lpc_init(struct device *dev)
@@ -114,11 +35,12 @@ static void lpc_init(struct device *dev)
        byte = pci_read_config8(dev, 0x4B);
        byte |= 1;
        pci_write_config8(dev, 0x4B, byte);
-       setup_ioapic();
+       /* Don't rename IO APIC */
+       setup_ioapic(IO_APIC_ADDR, 0);
 
        /* posted memory write enable */
        byte = pci_read_config8(dev, 0x46);
-       pci_write_config8(dev, 0x46, byte | (1<<0)); 
+       pci_write_config8(dev, 0x46, byte | (1<<0));
 
        /* Enable 5Mib Rom window */
        byte = pci_read_config8(dev, 0x43);
@@ -143,11 +65,11 @@ static void lpc_init(struct device *dev)
        pci_write_config8(dev, 0x40, byte);
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
-       if (nmi_option) {                       
+       if (nmi_option) {
                byte |= (1 << 7); /* set NMI */
                pci_write_config8(dev, 0x40, byte);
        }
-       
+
        /* Initialize the real time clock */
        rtc_init(0);
 
@@ -179,20 +101,14 @@ static void amd8111_lpc_read_resources(device_t dev)
                     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void amd8111_lpc_enable_resources(device_t dev)
-{
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-       pci_write_config32(dev, 0x70, 
+       pci_write_config32(dev, 0x70,
                           ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -203,7 +119,7 @@ static struct pci_operations lops_pci = {
 static struct device_operations lpc_ops  = {
        .read_resources   = amd8111_lpc_read_resources,
        .set_resources    = pci_dev_set_resources,
-       .enable_resources = amd8111_lpc_enable_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init             = lpc_init,
        .scan_bus         = scan_static_bus,
        .enable           = amd8111_enable,