- Bump the LinuxBIOS major version

[coreboot.git] / src / southbridge / amd / amd8111 / amd8111_ide.c

diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c
index f3516069897131edf02034b19405d6da71962113..167484401b1dc136c486cd65527798c07b2e4bd0 100644 (file)
--- a/src/southbridge/amd/amd8111/amd8111_ide.c
+++ b/src/southbridge/amd/amd8111/amd8111_ide.c
@@ -3,26 +3,25 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include "amd8111.h"
 
 static void ide_init(struct device *dev)
 {
-
+       struct southbridge_amd_amd8111_config *conf;
        /* Enable ide devices so the linux ide driver will work */
        uint16_t word;
-       int enable_a=1, enable_b=1;
-
+       uint8_t byte;
+       conf = dev->chip_info;
 
-        printk_debug("ide_init\n");
-
-       pci_read_config_word(dev, 0x40, &word);
+       word = pci_read_config16(dev, 0x40);
        /* Ensure prefetch is disabled */
        word &= ~((1 << 15) | (1 << 13));
-       if (enable_b) {
+       if (conf->ide1_enable) {
                /* Enable secondary ide interface */
                word |= (1<<0);
                printk_debug("IDE1 ");
        }
-       if (enable_a) {
+       if (conf->ide0_enable) {
                /* Enable primary ide interface */
                word |= (1<<1);
                printk_debug("IDE0 ");
@@ -31,30 +30,32 @@ static void ide_init(struct device *dev)
        word |= (1<<12);
        word |= (1<<14);
 
-       pci_write_config_word(dev, 0x40, word);
+       pci_write_config16(dev, 0x40, word);
 
-       word = 0x0f;
-       pci_write_config_word(dev, 0x42, word);
 
-       /* The AMD768 has a bug where the BM DMA address must be
-        * 256 byte aligned while it is only 16 bytes long.
-        * Hard code this to a valid address below 0x1000
-        * where automatic port address assignment starts.
-        * FIXME: I assume the 8111 does the same thing. We should
-        * clarify. stepan@suse.de
-        */
-       pci_write_config_dword(dev, 0x20, 0xf01);
+        byte = 0x20 ; // Latency: 64-->32
+        pci_write_config8(dev, 0xd, byte);
 
-       pci_write_config_dword(dev, 0x48, 0x205e5e5e);
-       word = 0x06a;
-       pci_write_config_word(dev, 0x4c, word);
+       word = 0x0f;
+       pci_write_config16(dev, 0x42, word);
 }
 
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+       pci_write_config32(dev, 0x70, 
+               ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+       .set_subsystem = lpci_set_subsystem,
+};
 static struct device_operations ide_ops  = {
-       .read_resources = pci_dev_read_resources,
-       .set_resources  = pci_dev_set_resources,
-       .init = ide_init,
-       .scan_bus = 0,
+       .read_resources   = pci_dev_read_resources,
+       .set_resources    = pci_dev_set_resources,
+       .enable_resources = pci_dev_enable_resources,
+       .init             = ide_init,
+       .scan_bus         = 0,
+       .enable           = amd8111_enable,
+       .ops_pci          = &lops_pci
 };
 
 static struct pci_driver ide_driver __pci_driver = {