We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / northbridge / via / vx800 / vx800.h

diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h
index f23974342e322429e8d17d2c57c66950e89977b2..ad84b104b9e37d7048f95336ee4ce6f89c8f9b80 100644 (file)
--- a/src/northbridge/via/vx800/vx800.h
+++ b/src/northbridge/via/vx800/vx800.h
@@ -20,11 +20,23 @@
 #ifndef VX800_H
 #define  VX800_H 1
 
-#ifndef __ROMCC__
-static void vx800_noop()
+#ifndef __PRE_RAM__
+#include <device/device.h>
+static inline void vx800_noop(device_t dev)
 {
 }
 #endif
+
+#ifdef __PRE_RAM__
+/* vx800_early_smbus.c */
+struct mem_controller;
+void enable_smbus(void);
+void smbus_fixup(const struct mem_controller *mem_ctrl);
+
+/* vx800_early_serial.c */
+void enable_vx800_serial(void);
+#endif
+
 //#define REV_B0 0x10
 #define REV_B1 0x11
 //#define REV_B2 0x12
@@ -108,7 +120,6 @@ static void vx800_noop()
 #define SB_EHCI_REG 0,0x10, 4,
 
 #define VX800SB_APIC_ID                        0x4
-#define VX800SB_APIC_BASE              0xfec00000ULL
 #define VX800SB_APIC_DATA_OFFSET             0x10
 #define VX800SB_APIC_ENTRY_NUMBER 0x40