#include <string.h>
#include <bitops.h>
#include <cpu/cpu.h>
+#include <boot/tables.h>
#include "chip.h"
#include "i945.h"
+#include <arch/coreboot_tables.h>
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+ device_t dev;
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (!dev)
+ return 0;
+
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: // 256MB
+ *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: // 128M
+ *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: // 64M
+ *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* IDG memory */
+uint64_t uma_memory_base=0, uma_memory_size=0;
+
+int add_northbridge_resources(struct lb_memory *mem)
+{
+ u32 pcie_config_base, pcie_config_size;
+
+ printk_debug("Adding UMA memory area\n");
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ uma_memory_base, uma_memory_size);
+
+ printk_debug("Adding PCIe config bar\n");
+ get_pcie_bar(&pcie_config_base, &pcie_config_size);
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ pcie_config_base, pcie_config_size);
+
+ return 0;
+}
static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
unsigned long sizek)
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffUL;
- resource->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffffffUL;
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
return tolm;
}
-#if HAVE_HIGH_TABLES==1
-#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
-uint64_t uma_memory_base=0, uma_memory_size=0;
static void pci_domain_set_resources(device_t dev)
{
uint16_t reg16;
unsigned long long tomk;
+ /* Can we find out how much memory we can use at most
+ * this way?
+ */
pci_tolm = find_pci_tolm(&dev->link[0]);
+ printk_debug("pci_tolm: 0x%x\n", pci_tolm);
printk_spew("Base of stolen memory: 0x%08x\n",
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
assign_resources(&dev->link[0]);
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE * 1024;
#endif
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
+ * See e7525/northbridge.c for an example.
*/
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
- printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
- resource->base, (resource->base + resource->size));
+ printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+ (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
}
static void mc_set_resources(device_t dev)
{
- struct resource *resource, *last;
+ struct resource *resource;
/* Report the PCIe BAR */
- last = &dev->resource[dev->resources];
resource = find_resource(dev, 0xcf);
if (resource) {
report_resource_stored(dev, resource, "<mmconfig>");
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
}
+#if CONFIG_HAVE_ACPI_RESUME
+extern u8 acpi_slp_type;
+
+static void northbridge_init(struct device *dev)
+{
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ printk_debug("Normal boot.\n");
+ acpi_slp_type=0;
+ break;
+ case 0xcafed00d:
+ printk_debug("S3 Resume.\n");
+ acpi_slp_type=3;
+ break;
+ default:
+ printk_debug("Unknown boot method, assuming normal.\n");
+ acpi_slp_type=0;
+ break;
+ }
+}
+#endif
+
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
.read_resources = mc_read_resources,
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = 0,
+#if CONFIG_HAVE_ACPI_RESUME
+ .init = northbridge_init,
+#endif
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
projects / coreboot.git / blobdiff