* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de>
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
* Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
*/
#include <spd.h>
-#include <sdram_mode.h>
#include <delay.h>
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
#include "i82810.h"
+#include "raminit.h"
/*-----------------------------------------------------------------------------
Macros and definitions.
-----------------------------------------------------------------------------*/
-/* Uncomment this to enable debugging output. */
-// #define DEBUG_RAM_SETUP 1
-
/* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all
+ * debugging code with ROMCC
+ */
+#if CONFIG_DEBUG_RAM_SETUP
#define PRINT_DEBUG(x) print_debug(x)
#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
-#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+// no dump_pci_device in src/northbridge/intel/i82810/
+// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+#define DUMPNORTH()
#else
#define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x)
#define RAM_COMMAND_MRS 0x6 /* Mode register set */
#define RAM_COMMAND_CBR 0x7 /* CBR */
+/*
+ * This table is used to translate the value read from SPD Byte 31 to a value
+ * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
+ * northbridges have some sort of simple calculation that can be done for this,
+ * I haven't yet figured out one for this northbridge. Until someone does,
+ * this table is necessary.
+ */
+static const u8 translate_spd_to_i82810[] = {
+ /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
+ * side can't be either, at least for now.
+ */
+ /* TODO: For above case, only use the other side if > 4MB, and get some
+ * of these DIMMs to test it with. Same for unsupported 128/x sizes.
+ */
+
+ /* SPD Byte 31 Memory Size [Side 1/2] */
+ 0xff, /* 0x01 No memory */
+ 0xff, /* 0x01 4/0 */
+ 0x01, /* 0x02 8/0 */
+ 0xff, /* 0x03 8/4 */
+ 0x04, /* 0x04 16/0 or 16 */
+ 0xff, /* 0x05 16/4 */
+ 0x05, /* 0x06 16/8 */
+ 0xff, /* 0x07 Invalid */
+ 0x07, /* 0x08 32/0 or 32 */
+ 0xff, /* 0x09 32/4 */
+ 0xff, /* 0x0A 32/8 */
+ 0xff, /* 0x0B Invalid */
+ 0x08, /* 0x0C 32/16 */
+ 0xff, 0xff, 0xff, /* 0x0D-0F Invalid */
+ 0x0a, /* 0x10 64/0 or 64 */
+ 0xff, /* 0x11 64/4 */
+ 0xff, /* 0x12 64/8 */
+ 0xff, /* 0x13 Invalid */
+ 0xff, /* 0x14 64/16 */
+ 0xff, 0xff, 0xff, /* 0x15-17 Invalid */
+ 0x0b, /* 0x18 64/32 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */
+ 0x0d, /* 0x20 128/0 or 128 */
+ /* These configurations are not supported by the i810 */
+ 0xff, /* 0x21 128/4 */
+ 0xff, /* 0x22 128/8 */
+ 0xff, /* 0x23 Invalid */
+ 0xff, /* 0x24 128/16 */
+ 0xff, 0xff, 0xff, /* 0x25-27 Invalid */
+ 0xff, /* 0x28 128/32 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */
+ 0x0e, /* 0x30 128/64 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, /* 0x31-3f Invalid */
+ 0x0f, /* 0x40 256/0 or 256 */
+ /* Anything larger is not supported by the 82810. */
+};
+
/*
* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
* Note that 2 is a value which the DRP should never be programmed to.
SDRAM configuration functions.
-----------------------------------------------------------------------------*/
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
/**
* Send the specified RAM command to all DIMMs.
*
drp = (drp >> (i * 4)) & 0x0f;
dimm_size = translate_i82810_to_mb[drp];
- addr = (dimm_start * 1024 * 1024) + addr_offset;
if (dimm_size) {
+ addr = (dimm_start * 1024 * 1024) + addr_offset;
+#if HAVE_ENOUGH_REGISTERS
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
+#endif
read32(addr);
}
dimm_bank = translate_i82810_to_bank[drp];
- addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
if (dimm_bank) {
+ addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
+#if HAVE_ENOUGH_REGISTERS
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
-
+ PRINT_DEBUG("\n");
+#endif
read32(addr);
}
if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex8(dimm_size * 4);
- print_debug("MB\r\n");
+ print_debug("MB\n");
/* The i810 can't handle DIMMs larger than 128MB per
* side. This will fail if the DIMM uses a
*/
if (dimm_size > 32) {
print_err("DIMM row sizes larger than 128MB not"
- "supported on i810\r\n");
+ "supported on i810\n");
print_err
- ("Attempting to treat as 128MB DIMM\r\n");
+ ("Attempting to treat as 128MB DIMM\n");
dimm_size = 32;
}
print_debug("After translation, dimm_size is 0x");
print_debug_hex8(dimm_size);
- print_debug("\r\n");
+ print_debug("\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
0xff) {
- print_debug("DIMM is dual-sided\r\n");
+ print_debug("DIMM is dual-sided\n");
dimm_size += 2;
}
} else {
print_debug("No DIMM found in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* If there's no DIMM in the slot, set value to 0. */
dimm_size = 0x00;
print_debug("DRP calculated to 0x");
print_debug_hex8(drp);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
}
SPD_NUM_DIMM_BANKS) > 1;
d1.ss = !d1.ds;
}
-
+
buff_sc = 0;
/* Tame the beast... */
buff_sc |= 1 << 14;
if (!d0.size && d1.size)
buff_sc |= 1 << 15;
-
+
print_debug("BUFF_SC calculated to 0x");
print_debug_hex16(buff_sc);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
}
Public interface.
-----------------------------------------------------------------------------*/
-static void sdram_set_registers(void)
+void sdram_set_registers(void)
{
u8 reg8;
- u16 reg16, did;
+ u16 did;
did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
/* Ideally, this should be R/W for as many ranges as possible. */
pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
-
+
/* Set size for onboard-VGA framebuffer. */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
reg8 &= 0x3f; /* Disable graphics (for now). */
pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
}
-static void sdram_set_spd_registers(void)
+void sdram_set_spd_registers(void)
{
spd_set_dram_size();
set_dram_buffer_strength();
/**
* Enable SDRAM.
*/
-static void sdram_enable(void)
+void sdram_enable(void)
{
int i;
/* 1. Apply NOP. */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation (enables refresh at 15.6usec). */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
projects / coreboot.git / blobdiff