Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.

[coreboot.git] / src / northbridge / intel / i82810 / i82810.h

diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h
index 0b406cead41477f4a26a0192541c0ce3d76889da..66957547633cad875a6cf87f22eb07c8030910b3 100644 (file)
--- a/src/northbridge/intel/i82810/i82810.h
+++ b/src/northbridge/intel/i82810/i82810.h
@@ -1,7 +1,7 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,6 +18,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef NORTHBRIDGE_INTEL_I82810_I82810_H
+#define NORTHBRIDGE_INTEL_I82810_I82810_H
+
 /*
  * Datasheet:
  *   - Name: Intel 810 Chipset:
@@ -30,30 +33,20 @@
 /*
  * PCI Configuration Registers.
  *
- * Any addresses between 0x00 and 0xff not listed below are reserved and
+ * Any addresses between 0x50 and 0xff not listed below are reserved and
  * should not be touched.
  */
 
-#define VID    0x00 /* Vendor Identification   */
-#define DID    0x02 /* Device Identification   */
-#define PCICMD 0x04 /* PCI Command Register    */
-#define PCISTS 0x06 /* PCI Status Register     */
-#define RID    0x08 /* Revision Identification */
-#define SUBC   0x0a /* Sub-Class Code          */
-#define BCC    0x0b /* Base Class Code         */
-#define MLT    0x0d /* Master Latency Timer    */
-#define HDR    0x0e /* Header Type             */
-#define SVID   0x2c /* Subsystem Vendor Identification  */
-#define SID    0x2e /* Subsystem Identification         */
-#define CAPPTR 0x34 /* Capabilities Pointer             */
+#define GMCHCFG        0x50            /* GMCH Configuration */
+#define PAMR   0x51            /* Programmable Attributes */
+#define DRP    0x52            /* DRAM Row Population */
+#define DRAMT  0x53            /* DRAM Timing */
+#define FDHC   0x58            /* Fixed DRAM Hole Control */
+#define SMRAM  0x70            /* System Management RAM Control */
+#define MISSC  0x72            /* Miscellaneous Control */
+#define MISSC2 0x80            /* Miscellaneous Control 2 */
+#define BUFF_SC        0x92            /* System Memory Buffer Strength Control */
+
+int smbus_read_byte(u8 device, u8 address);
 
-/* TODO: Descriptions  */
-#define GMCHCFG        0x50
-#define PAM    0x51
-#define DRP    0x52
-#define DRAMT  0x53
-#define FDHC   0x58
-#define SMRAM  0x70 /* System Management RAM Control */
-#define MISSC  0x72
-#define MISSC2 0x80
-#define BUFF_SC        0x92
+#endif