Report GSE chipset and warn if the code has been compiled for the wrong chipset.

[coreboot.git] / src / northbridge / intel / i3100 / raminit.c

diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 78e7b72f1f65498a7be5dda3dcf599d8af0d501f..86e610feb3e4ade319d5c7f929a46f362a9947f3 100644 (file)
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -973,12 +973,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        print_debug("Starting SDRAM Enable\n");
 
        /* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
        pci_write_config32(ctrl->f0, DRM,
-               0x00410000 | DIMM_MAP_LOGICAL);
-#else
-       pci_write_config32(ctrl->f0, DRM, 0x00411248);
-#endif
+               0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
        /* set dram type and Front Side Bus freq. */
        drc = spd_set_dram_controller_mode(ctrl, mask);
        if( drc == 0) {
@@ -1212,7 +1208,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        pci_write_config16(ctrl->f0, MCHSCRB, data16);
 
        /* The memory is now setup, use it */
-#if CONFIG_USE_DCACHE_RAM == 0
+#if CONFIG_CACHE_AS_RAM == 0
        cache_lbmem(MTRR_TYPE_WRBACK);
 #endif
 }