DDR3 support for AMD Fam10.

[coreboot.git] / src / northbridge / amd / amdmct / wrappers / mcti_d.c

diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index f2107c95d1c6728332c3d541f61f733fc72be6c3..a4a87fca01dc7cdacd2ae9f30147411d0ea58c40 100644 (file)
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -19,7 +19,7 @@
 
 /* Call-backs */
 #include <delay.h>
-u16 mctGet_NVbits(u8 index)
+static u16 mctGet_NVbits(u8 index)
 {
        u16 val = 0;
 
@@ -27,8 +27,10 @@ u16 mctGet_NVbits(u8 index)
        case NV_PACK_TYPE:
 #if CONFIG_CPU_SOCKET_TYPE == 0x10     /* Socket F */
                val = 0;
-#elif CONFIG_CPU_SOCKET_TYPE == 0x11   /* AM2r2 */
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11   /* AM3 */
                val = 1;
+#elif CONFIG_CPU_SOCKET_TYPE == 0x13   /* ASB2 */
+               val = 4;
 //#elif SYSTEM_TYPE == MOBILE
 //             val = 2;
 #endif
@@ -223,106 +225,112 @@ u16 mctGet_NVbits(u8 index)
 }
 
 
-void mctHookAfterDIMMpre(void)
+static void mctHookAfterDIMMpre(void)
 {
 }
 
 
-void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
        pDCTstat->PresetmaxFreq = 400;
 }
 
-
-void mctAdjustAutoCycTmg(void)
+#ifdef UNUSED_CODE
+static void mctAdjustAutoCycTmg(void)
 {
 }
+#endif
+
 
-void mctAdjustAutoCycTmg_D(void)
+static void mctAdjustAutoCycTmg_D(void)
 {
 }
 
 
-void mctHookAfterAutoCycTmg(void)
+static void mctHookAfterAutoCycTmg(void)
 {
 }
 
 
-void mctGetCS_ExcludeMap(void)
+static void mctGetCS_ExcludeMap(void)
 {
 }
 
 
-void mctHookAfterAutoCfg(void)
+static void mctHookAfterAutoCfg(void)
 {
 }
 
 
-void mctHookAfterPSCfg(void)
+static void mctHookAfterPSCfg(void)
 {
 }
 
 
-void mctHookAfterHTMap(void)
+static void mctHookAfterHTMap(void)
 {
 }
 
 
-void mctHookAfterCPU(void)
+static void mctHookAfterCPU(void)
 {
 }
 
 
-void mctSaveDQSSigTmg_D(void)
+static void mctSaveDQSSigTmg_D(void)
 {
 }
 
 
-void mctGetDQSSigTmg_D(void)
+static void mctGetDQSSigTmg_D(void)
 {
 }
 
 
-void mctHookBeforeECC(void)
+static void mctHookBeforeECC(void)
 {
 }
 
 
-void mctHookAfterECC(void)
+static void mctHookAfterECC(void)
 {
 }
 
-
-void mctInitMemGPIOs_A(void)
+#ifdef UNUSED_CODE
+static void mctInitMemGPIOs_A(void)
 {
 }
+#endif
 
 
-void mctInitMemGPIOs_A_D(void)
+static void mctInitMemGPIOs_A_D(void)
 {
 }
 
 
-void mctNodeIDDebugPort_D(void)
+static void mctNodeIDDebugPort_D(void)
 {
 }
 
 
-void mctWarmReset(void)
+#ifdef UNUSED_CODE
+static void mctWarmReset(void)
 {
 }
+#endif
+
 
-void mctWarmReset_D(void)
+static void mctWarmReset_D(void)
 {
 }
 
 
-void mctHookBeforeDramInit(void)
+static void mctHookBeforeDramInit(void)
 {
 }
 
 
-void mctHookAfterDramInit(void)
+static void mctHookAfterDramInit(void)
 {
 }
 
@@ -330,7 +338,7 @@ static void coreDelay (void);
 
 
 /* Erratum 350 */
-void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
+static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
 {
        u8 u8Channel;
        u8 u8Receiver;
@@ -347,68 +355,81 @@ void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
                        u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
 
                        if(!u8Valid) {  /* Address not supported on current CS */
-                               print_t("vErrara350: Address not supported on current CS\n");
+                               print_t("vErrata350: Address not supported on current CS\n");
                                continue;
                        }
-                       print_t("vErrara350: dummy read \n");
+                       print_t("vErrata350: dummy read \n");
                        read32_fs(u32Addr);
                }
        }
 
-       print_t("vErrara350: step 2a\n");
+       print_t("vErrata350: step 2a\n");
 
        /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
        u32DctDev = pDCTstat->dev_dct;
-       Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00008000);
+       Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
        /*                                                ^--- value
-                                               ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register
+                                               ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
                                         ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
 
        if(!pDCTstat->GangedMode) {
-               print_t("vErrara350: step 2b\n");
-               Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00008000);
+               print_t("vErrata350: step 2b\n");
+               Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
                /*                                                ^--- value
-                                                       ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register
+                                                       ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
                                                ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
        }
 
-       print_t("vErrara350: step 3\n");
+       print_t("vErrata350: step 3\n");
        /* 3. Wait at least 300 nanoseconds. */
        coreDelay();
 
-       print_t("vErrara350: step 4\n");
+       print_t("vErrata350: step 4\n");
        /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
-       Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00000000);
+       Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
 
        if(!pDCTstat->GangedMode) {
-               print_t("vErrara350: step 4b\n");
-               Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00000000);
+               print_t("vErrata350: step 4b\n");
+               Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
        }
 
-       print_t("vErrara350: step 5\n");
+       print_t("vErrata350: step 5\n");
        /* 5. Wait at least 2 microseconds. */
        coreDelay();
 
 }
 
 
-void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
+static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 {
-       if (pDCTstatA->LogicalCPUID & AMD_RB_C2) {
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+       if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
                vErrata350(pMCTstat, pDCTstatA);
        }
+#endif
+}
+
+static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
+{
+       if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
+               if (pDCTstatA->Status & (1 << SB_Registered)) {
+                       val ++;
+               }
+       }
+       return val;
 }
 
-void mctHookAfterAnyTraining(void)
+static void mctHookAfterAnyTraining(void)
 {
 }
 
-u32 mctGetLogicalCPUID_D(u8 node)
+static u32 mctGetLogicalCPUID_D(u8 node)
 {
        return mctGetLogicalCPUID(node);
 }
 
-u8 mctSetNodeBoundary_D(void)
+static u8 mctSetNodeBoundary_D(void)
 {
        return 0;
 }
+