/* Call-backs */
#include <delay.h>
-u16 mctGet_NVbits(u8 index)
+static u16 mctGet_NVbits(u8 index)
{
u16 val = 0;
case NV_PACK_TYPE:
#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* Socket F */
val = 0;
-#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2r2 */
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM3 */
val = 1;
+#elif CONFIG_CPU_SOCKET_TYPE == 0x13 /* ASB2 */
+ val = 4;
//#elif SYSTEM_TYPE == MOBILE
// val = 2;
#endif
}
-void mctHookAfterDIMMpre(void)
+static void mctHookAfterDIMMpre(void)
{
}
-void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
pDCTstat->PresetmaxFreq = 400;
}
-
-void mctAdjustAutoCycTmg(void)
+#ifdef UNUSED_CODE
+static void mctAdjustAutoCycTmg(void)
{
}
+#endif
+
-void mctAdjustAutoCycTmg_D(void)
+static void mctAdjustAutoCycTmg_D(void)
{
}
-void mctHookAfterAutoCycTmg(void)
+static void mctHookAfterAutoCycTmg(void)
{
}
-void mctGetCS_ExcludeMap(void)
+static void mctGetCS_ExcludeMap(void)
{
}
-void mctHookAfterAutoCfg(void)
+static void mctHookAfterAutoCfg(void)
{
}
-void mctHookAfterPSCfg(void)
+static void mctHookAfterPSCfg(void)
{
}
-void mctHookAfterHTMap(void)
+static void mctHookAfterHTMap(void)
{
}
-void mctHookAfterCPU(void)
+static void mctHookAfterCPU(void)
{
}
-void mctSaveDQSSigTmg_D(void)
+static void mctSaveDQSSigTmg_D(void)
{
}
-void mctGetDQSSigTmg_D(void)
+static void mctGetDQSSigTmg_D(void)
{
}
-void mctHookBeforeECC(void)
+static void mctHookBeforeECC(void)
{
}
-void mctHookAfterECC(void)
+static void mctHookAfterECC(void)
{
}
-
-void mctInitMemGPIOs_A(void)
+#ifdef UNUSED_CODE
+static void mctInitMemGPIOs_A(void)
{
}
+#endif
-void mctInitMemGPIOs_A_D(void)
+static void mctInitMemGPIOs_A_D(void)
{
}
-void mctNodeIDDebugPort_D(void)
+static void mctNodeIDDebugPort_D(void)
{
}
-void mctWarmReset(void)
+#ifdef UNUSED_CODE
+static void mctWarmReset(void)
{
}
+#endif
+
-void mctWarmReset_D(void)
+static void mctWarmReset_D(void)
{
}
-void mctHookBeforeDramInit(void)
+static void mctHookBeforeDramInit(void)
{
}
-void mctHookAfterDramInit(void)
+static void mctHookAfterDramInit(void)
{
}
/* Erratum 350 */
-void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
+static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
{
u8 u8Channel;
u8 u8Receiver;
}
-void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
+static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
{
- if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) {
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+ if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
vErrata350(pMCTstat, pDCTstatA);
}
+#endif
+}
+
+static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
+{
+ if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
+ if (pDCTstatA->Status & (1 << SB_Registered)) {
+ val ++;
+ }
+ }
+ return val;
}
-void mctHookAfterAnyTraining(void)
+static void mctHookAfterAnyTraining(void)
{
}
-u32 mctGetLogicalCPUID_D(u8 node)
+static u32 mctGetLogicalCPUID_D(u8 node)
{
return mctGetLogicalCPUID(node);
}
-u8 mctSetNodeBoundary_D(void)
+static u8 mctSetNodeBoundary_D(void)
{
return 0;
}
+