Fix ECC disable option for AMD Fam10 DDR2 and DDR3.

[coreboot.git] / src / northbridge / amd / amdmct / mct_ddr3 / mctecc_d.c

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 288093c73b76e2e3d9f5f16621ae3149e856b05b..6107e80d25dfd5bbe4e4c2cf9a39626047c1d991 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -56,7 +56,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
  * guarantee that the NB scrubs the entire dram on its node. Do do this, we
  * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR
  * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all
- * Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do
+ * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do
  * this efficiently, we need only to sample one of the nodes, the node with the
  * largest ammount of dram populated is the one which will take the longest amount
  * of time (the scrub rate is set to max, the same rate, on all nodes).  So,
@@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                                        LDramECC = isDramECCEn_D(pDCTstat);
                                        if(pDCTstat->ErrCode != SC_RunningOK) {
                                                pDCTstat->Status &=  ~(1 << SB_ECCDIMMs);
-                                               if (OB_NBECC) {
+                                               if (!OB_NBECC) {
                                                        pDCTstat->ErrStatus |= (1 << SB_DramECCDis);
                                                }
                                                AllECC = 0;
@@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                                                Set_NB32(dev, reg, val);
                                                DCTMemClr_Init_D(pMCTstat, pDCTstat);
                                                MemClrECC = 1;
+                                               printk(BIOS_DEBUG, "  ECC enabled on node: %02x\n", Node);
                                        }
                                }       /* this node has ECC enabled dram */
                        } else {
@@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
                setSyncOnUnEccEn_D(pMCTstat, pDCTstatA);
 
        mctHookAfterECC();
+       for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
+               struct DCTStatStruc *pDCTstat;
+               pDCTstat = pDCTstatA + Node;
+               if (NodePresent_D(Node)) {
+                       printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node);
+                       printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status);
+                       printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus);
+                       printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode);
+                       printk(BIOS_DEBUG, "ECCInit: Done\n");
+               }
+       }
        return MemClrECC;
 }