Fix ECC disable option for AMD Fam10 DDR2 and DDR3.

[coreboot.git] / src / northbridge / amd / amdmct / mct / mctpro_d.c

diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index a2d08d194e75189a2b0c452615422ab8ee494ac6..1539a880eb63e9f5a5524a9291fd63ed667fbc82 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -134,7 +134,7 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat,
 
        /* Bug#15880: Determine validity of reset settings for DDR PHY timing
         *   regi..
-        * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training.
+        * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training.
         */
 
        u32 dev;