Fix ECC disable option for AMD Fam10 DDR2 and DDR3.

[coreboot.git] / src / northbridge / amd / amdmct / mct / mct.h

diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h
index 2ddd5da7bc8e1adf732bcc2df8f659612f1f4fe0..2f92c15d0ebdfc8ed8b00ec700493562fae264cc 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct.h
+++ b/src/northbridge/amd/amdmct/mct/mct.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
@@ -110,7 +110,7 @@
 #define Mod64BitMux    4               /* func 2, offset A0h, bit 4 */
 #define DisableJitter  1               /* func 2, offset A0h, bit 1 */
 #define DramEnabled    9               /* func 2, offset A0h, bit 9 */
-#define SyncOnUcEccEn  2               /* fun 3, offset 44h, bit 2 */
+#define SyncOnUcEccEn  2               /* func 3, offset 44h, bit 2 */
 
 /*=============================================================================
        Jedec DDR II
@@ -349,7 +349,7 @@ struct DCTStatStruc {               /* A per Node structure*/
        u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/
        u16 DimmDRPresent;      /* Bitmap indicating that Dual Rank Dimms are present*/
        u16 DimmPlPresent;      /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/
-       u16 ChannelTrainFail;   /* Bitmap showing the chanel informaiton about failed Chip Selects*/
+       u16 ChannelTrainFail;   /* Bitmap showing the channel information about failed Chip Selects*/
                                /* 0 in any bit field indicates Channel 0*/
                                /* 1 in any bit field indicates Channel 1*/
 };
@@ -496,20 +496,8 @@ struct DCTStatStruc {              /* A per Node structure*/
                                           0=disable
                                           1=enable*/
 
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED    8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED    8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED       8
-#endif
-
 
-// global function
+/* global function */
 u32 NodePresent(u32 Node);
 u32 Get_NB32n(struct DCTStatStruc *pDCTstat, u32 addrx);
 u32 Get_NB32(u32 addr); /* NOTE: extend addr to 32 bit for bus > 0 */
@@ -538,7 +526,6 @@ u32 SetUpperFSbase(u32 addr_hi);
 
 void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 
-unsigned amd_FD_support(void);
 void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 
 void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);