Drop console/console.c and pc80/serial.c from mainboards'

[coreboot.git] / src / mainboard / via / pc2500e / romstage.c

diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 9bfaefffc4dc5856cd9cd9025363bb41144f39fe..71d916a82d3efb488c7f0f59ce5455a394bf3051 100644 (file)
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -27,15 +27,13 @@
 #include <arch/hlt.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 
@@ -58,7 +56,7 @@ static const struct mem_controller ctrl = {
        .channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */
 };
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
        /* Enable multifunction for northbridge. */
        pci_write_config8(ctrl.d0f0, 0x4f, 0x01);