Winbond W83627HF: Use existing functions instead of open-coding.

[coreboot.git] / src / mainboard / via / epia-m700 / romstage.c

diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 2e51c958d047ae6229a7955ddf5f9453b5380a2b..85522c03d97e0d28089796f5d6361e679f6dd42e 100644 (file)
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -22,8 +22,6 @@
  * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch.
  */
 
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 #define PAYLOAD_IS_SEABIOS 0
 
 #include <stdint.h>
@@ -33,27 +31,22 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
+#include <lib.h>
 #include "northbridge/via/vx800/vx800.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <string.h>
-
 /* This file contains the board-special SI value for raminit.c. */
 #include "driving_clk_phase_data.c"
-
 #include "northbridge/via/vx800/raminit.h"
 #include "northbridge/via/vx800/raminit.c"
-
 #include "wakeup.h"
-
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 /*
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
@@ -392,7 +385,7 @@ void main(unsigned long bist)
         */
        pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
        /* EmbedComInit(); */
-       w83697hf_set_clksel_48(SERIAL_DEV);
+       w83697hf_set_clksel_48(DUMMY_DEV);
        w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        /* enable_vx800_serial(); */
@@ -456,17 +449,6 @@ void main(unsigned long bist)
        /* This fix does help vx800!, but vx855 doesn't need this. */
        /* smbus_fixup(&ctrl); */
 
-       if (bist == 0) {
-               /*
-                * CAR needs MTRR until memory is ok, so disable this
-                * early_mtrr_init() call.
-                */
-#if 0
-                print_debug("doing early_mtrr\n");
-                early_mtrr_init();
-#endif
-       }
-
        /* Halt if there was a built-in self test failure. */
        report_bist_failure(bist);
 
@@ -547,7 +529,7 @@ void main(unsigned long bist)
        /*
         * For coreboot most time of S3 resume is the same as normal boot,
         * so some memory area under 1M become dirty, so before this happen,
-        * I need to backup the content of mem to top-mem. 
+        * I need to backup the content of mem to top-mem.
         *
         * I will reserve the 1M top-men in LBIO table in coreboot_table.c
         * and recovery the content of 1M-mem in wakeup.c.
@@ -628,7 +610,7 @@ void main(unsigned long bist)
                );
 #endif
 
-               /* 
+               /*
                 * WAKE_MEM_INFO is inited in get_set_top_available_mem()
                 * in tables.c these two memcpy() not not be enabled if set
                 * the MTRR around this two lines.
@@ -680,8 +662,5 @@ void main(unsigned long bist)
                );
 #endif
        }
-
 #endif
-
 }
-