-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
{
#define SMBUS_HUB 0x18
int ret, i;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
#include "lib/generic_sdram.c"
/* tyan does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#define DIMM2 0x52
#define DIMM3 0x53
-#include "cpu/amd/car/copy_and_run.c"
+
#include "cpu/amd/car/post_cache_as_ram.c"
bsp_apicid = init_cpus(cpu_init_detectedx);
}
-
+
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
nodes = get_nodes();
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
-
+
enable_smbus();
memreset_setup();