run uart_init() from console_init, just like the other console initialization functions.

[coreboot.git] / src / mainboard / tyan / s2912 / romstage.c

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index aa6107637d1fda1ba53b1452d179db9b0dd16291..52a100c7dffe4af10be468e3294ae3f3cf268445 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -43,8 +43,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -61,7 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
@@ -131,16 +131,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        setup_mb_resource_map();
-       uart_init();
+
+       console_init();
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-       console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");