Remove lib/ramtest.c-include from all CAR boards.

[coreboot.git] / src / mainboard / tyan / s2912 / romstage.c

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index c525ab773c3f2067b1f7f8c28f4456582abf569f..2d3e12643e427d7ec48b23609e3c228541d0f075 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -38,8 +38,6 @@
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
-#define DBGP_DEFAULT 7
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -48,16 +46,14 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-#include "pc80/serial.c"
-#include "console/console.c"
-#if CONFIG_USBDEBUG_DIRECT
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
-#include "pc80/usbdebug_direct_serial.c"
+#include <pc80/mc146818rtc.h>
+
+#include <console/console.h>
+#if CONFIG_USBDEBUG
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -83,10 +79,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -102,12 +94,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
-
 #include "lib/generic_sdram.c"
 
 #include "resourcemap.c"
@@ -130,8 +119,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -143,8 +130,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
-       unsigned value;
        uint32_t dword;
        uint8_t byte;
 
@@ -160,21 +145,21 @@ static void sio_setup(void)
        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
        dword |= (1<<16);
        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
+                       // Node 0
                        (0xa<<3)|0, (0xa<<3)|2, 0, 0,
                        (0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                       // Node 1
                        (0xa<<3)|4, (0xa<<3)|6, 0, 0,
                        (0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
        };
 
-       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+               + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
@@ -204,9 +189,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG_DIRECT
-       mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+       early_usbdebug_init();
 #endif
        console_init();
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -256,6 +241,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        }
 #endif
 
+       init_timer(); // Need to use TMICT to synconize FID/VID
+
        needs_reset |= optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        needs_reset |= mcp55_early_setup_x();
@@ -273,15 +260,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        enable_smbus();
 
-       memreset_setup();
-
-       //do we need apci timer, tsc...., only debug need it for better output
        /* all ap stopped? */
-//     init_timer(); // Need to use TMICT to synconize FID/VID
 
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-