This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / mainboard / tyan / s2912 / cache_as_ram_auto.c

diff --git a/src/mainboard/tyan/s2912/cache_as_ram_auto.c b/src/mainboard/tyan/s2912/cache_as_ram_auto.c
index 7c387b9bd0bb8457258d49309d9f44341d5a349f..5be6d82e9bb1814892a570e6c49209873ff25291 100644 (file)
--- a/src/mainboard/tyan/s2912/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2912/cache_as_ram_auto.c
@@ -39,7 +39,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -56,7 +56,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -79,7 +79,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 #include "cpu/x86/bist.h"
 
@@ -150,7 +150,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -219,7 +219,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
                );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
        __asm__ volatile ("jmp __fallback_image"
                : /* outputs */
                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -232,21 +232,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+    #if CONFIG_USE_FAILOVER_IMAGE==1
        failover_process(bist, cpu_init_detectedx);
     #else
        real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
        failover_process(bist, cpu_init_detectedx);
     #endif
        real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -259,7 +259,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
        };
 
-       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
@@ -268,7 +268,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
        }
 
-       w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
        setup_mb_resource_map();
 
@@ -287,7 +287,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 #endif
        setup_coherent_ht_domain(); // routing table and start other core0