Rename almost all occurences of LinuxBIOS to coreboot.

[coreboot.git] / src / mainboard / tyan / s2885 / Options.lb

diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
index 5ca7df6a344617fe445f167841e87f9a72d07ee9..254483d3ad0f703e0a3e2bfe0ddcc20161476562 100644 (file)
--- a/src/mainboard/tyan/s2885/Options.lb
+++ b/src/mainboard/tyan/s2885/Options.lb
@@ -16,8 +16,10 @@ uses ROM_SECTION_SIZE
 uses ROM_IMAGE_SIZE
 uses ROM_SECTION_SIZE
 uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 uses _ROMBASE
 uses XIP_ROM_SIZE
@@ -33,7 +35,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -63,6 +65,13 @@ uses ENABLE_APIC_EXT_ID
 uses APIC_ID_OFFSET
 uses LIFT_BSP_APIC_ID
 
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses CONFIG_LB_MEM_TOPK
+
 ###
 ### Build options
 ###
@@ -85,7 +94,7 @@ default FALLBACK_SIZE=0x40000
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -107,7 +116,7 @@ default HAVE_MP_TABLE=1
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -125,6 +134,18 @@ default CONFIG_LOGICAL_CPUS=1
 #CHIP_NAME ?
 default CONFIG_CHIP_NAME=1
 
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0a
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+default HT_CHAIN_END_UNITID_BASE=0x06
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+##only offset for SB chain?, default is yes(1)
+#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 
@@ -159,10 +180,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -181,14 +202,14 @@ default HEAP_SIZE=0x4000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
 ##
-default CONFIG_ROM_STREAM = 1
+default CONFIG_ROM_PAYLOAD = 1
 
 ###
 ### Defaults of options that you may want to override in the target config file
@@ -230,7 +251,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately