Rename almost all occurences of LinuxBIOS to coreboot.

[coreboot.git] / src / mainboard / tyan / s2885 / Config.lb

diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index f6ea627f8bb62b9fdeb04c824a79a06d5fc71b5b..a6c044929091c8f8366029e209a986cb8f6359d4 100644 (file)
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -41,10 +41,9 @@ arch i386 end
 driver mainboard.o
 
 #dir /drivers/si/3114
-
+object get_bus_conf.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 if USE_DCACHE_RAM
 
@@ -91,11 +90,15 @@ end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
+
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
@@ -107,7 +110,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
@@ -137,7 +140,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###