This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / mainboard / tyan / s2880 / cache_as_ram_auto.c

diff --git a/src/mainboard/tyan/s2880/cache_as_ram_auto.c b/src/mainboard/tyan/s2880/cache_as_ram_auto.c
index 3ada300474f391029291227461379d7fb2210035..bfb89116c6355091c57721673d158c8cf24ab158 100644 (file)
--- a/src/mainboard/tyan/s2880/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2880/cache_as_ram_auto.c
@@ -2,11 +2,13 @@
 #define __ROMCC__
  
 #include <stdint.h>
+#include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -14,17 +16,13 @@
 #include "ram/ramtest.c"
 
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
@@ -37,31 +35,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 static void memreset_setup(void)
 {
@@ -93,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
@@ -112,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -164,7 +138,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         failover_process(bist, cpu_init_detectedx);
 #endif
         real_main(bist, cpu_init_detectedx);
@@ -197,14 +171,13 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        };
 
         int needs_reset;
-       unsigned cpu_reset = 0;
 
         if (bist == 0) {
                init_cpus(cpu_init_detectedx);
         }
 
        
-       w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -230,7 +203,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        enable_smbus();
 
        memreset_setup();
-       sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+       sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
-       post_cache_as_ram(cpu_reset);
+       post_cache_as_ram();
 }