Drop console/console.c and pc80/serial.c from mainboards'
[coreboot.git] / src / mainboard / tyan / s2875 / romstage.c
index da9da07485ea3943a205248e4ddf0ec1f5ae954d..e074adb05667acf7ad5110021b56579c3ed9ccf0 100644 (file)
@@ -1,6 +1,4 @@
-#define ASSEMBLY 1
-#define __PRE_RAM__
+
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -11,8 +9,7 @@
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
@@ -27,7 +24,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -78,7 +75,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -137,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         setup_default_resource_map();
 
        needs_reset = setup_coherent_ht_domain();
-       
+
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
@@ -145,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
                if (needs_reset) {
-                       print_info("ht reset -\r\n");
+                       print_info("ht reset -\n");
                        soft_reset();
                }
 
@@ -157,3 +154,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();
 
 }
+