##
driver mainboard.o
+
+#dir /drivers/si/3114
+
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
+
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+end
+
+else
+
+makerule ./auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
##
## Romcc output
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
+end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+end
+
mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+
+ if CONFIG_USE_INIT
+ ldscript /cpu/amd/car/cache_as_ram.lds
+ end
+end
##
## Build our reset vector (This is where linuxBIOS is entered)
ldscript /cpu/x86/32bit/reset32.lds
end
+if USE_DCACHE_RAM
+else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
+end
##
## Include an id string (For safe flashing)
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+else
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
end
###
### O.k. We aren't just an intermediary anymore!
###
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
##
## Setup RAM
##
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
+
##
## Include the secondary Configuration files
##
-dir /pc80
-config chip.h
+if CONFIG_CHIP_NAME
+ config chip.h
+end
# sample config for tyan/s2850
-chip northbridge/amd/amdk8
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
device pci_domain 0 on
- device pci 18.0 on # LDT0
- # devices on link 2, link 2 == LDT 2
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 off end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # LDT0
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ #chip drivers/ati/ragexl
+ chip drivers/pci/onboard
+ device pci b.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x201
- io 0x62 = 0x330
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
end
end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 on end
- device pci 1.6 off end
- end
- end # device pci 18.0
-
- device pci 18.0 on end
- device pci 18.0 on end
-
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
-
- end
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
+ end # device pci 18.0
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
end
- end
+ end
end
projects / coreboot.git / blobdiff