v2/src romfs->cbfs rename

[coreboot.git] / src / mainboard / tyan / s1846 / Options.lb

diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb
index ebec984879f84f55706e1c5b66081de3682b62a4..e5ebc85be68a55294dd408ed1cb38b3941eeebb5 100644 (file)
--- a/src/mainboard/tyan/s1846/Options.lb
+++ b/src/mainboard/tyan/s1846/Options.lb
@@ -1,5 +1,5 @@
 ##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -19,6 +19,7 @@
 ##
 
 uses HAVE_MP_TABLE
+uses CONFIG_CBFS
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
@@ -30,7 +31,7 @@ uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses ARCH
 uses FALLBACK_SIZE
 uses STACK_SIZE
@@ -42,6 +43,7 @@ uses ROM_SECTION_SIZE
 uses ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 uses _ROMBASE
 uses _RAMBASE
@@ -71,7 +73,7 @@ default HAVE_MP_TABLE = 0
 default HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
+default HAVE_PIRQ_TABLE = 0
 default IRQ_SLOT_COUNT = 0             # Override this in targets/*/Config.lb.
 default MAINBOARD_VENDOR = "N/A"       # Override this in targets/*/Config.lb.
 default MAINBOARD_PART_NUMBER = "N/A"  # Override this in targets/*/Config.lb.
@@ -96,4 +98,9 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
+#
+# CBFS
+#
+#
+default CONFIG_CBFS=0
 end