Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / thomson / ip1000 / romstage.c

diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index 515059ac0971afa67bf25bc2fd7d6e281f17b88c..c9ec8a80b2630d01c45d18c832f3455eda9ba8f8 100644 (file)
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -37,24 +37,24 @@
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
 /**
  * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
  * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50), and the onboard memory is located in socket1 (0x51).
+ * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
+ * (0x51/DIMM1).
  */
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        int i;
 
-       if (device == 0x50) {
+       if (device == DIMM0) {
                return smbus_read_byte(device, address);
-       } else if (device == 0x51) {
+       } else if (device == DIMM1) {
                for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
                        if (spd_table[i].address == address)
                                return spd_table[i].data;
@@ -98,9 +98,8 @@ static void mb_early_setup(void)
 void main(unsigned long bist)
 {
        if (bist == 0) {
-               if (memory_initialized()) {
+               if (memory_initialized())
                        hard_reset();
-               }
        }
 
        /* Set southbridge and superio gpios */
@@ -125,8 +124,4 @@ void main(unsigned long bist)
 #if CONFIG_LLSHELL
        llshell();
 #endif
-       /* Check RAM. */
-       /* ram_check(0, 640 * 1024); */
-       /* ram_check(64512 * 1024, 65536 * 1024); */
 }
-