Re-integrate "USE_OPTION_TABLE" code.

[coreboot.git] / src / mainboard / supermicro / x6dhe_g2 / romstage.c

diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index f38f4e9b07ace97c4b6b664094b7b30dd3d570f5..7f20e0a697275a804f3dbcd93d53fb834a560e6d 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-#define __PRE_RAM__
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -7,10 +5,8 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -25,7 +21,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -44,10 +39,6 @@
 #define RECVENA_CONFIG  0x0708090a
 #define RECVENB_CONFIG  0x0708090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -55,21 +46,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
-
+#include "arch/i386/lib/stages.c"
 
 static void main(unsigned long bist)
 {
        /*
-        * 
-        * 
+        *
+        *
         */
        static const struct mem_controller mch[] = {
                {
                        .node_id = 0,
+                       /*
                        .f0 = PCI_DEV(0, 0x00, 0),
                        .f1 = PCI_DEV(0, 0x00, 1),
                        .f2 = PCI_DEV(0, 0x00, 2),
                        .f3 = PCI_DEV(0, 0x00, 3),
+                       */
                        .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
                        .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
 
@@ -80,7 +73,7 @@ static void main(unsigned long bist)
                /* Skip this if there was a built in self test failure */
                early_mtrr_init();
                if (memory_initialized()) {
-                       asm volatile ("jmp __cpu_reset");
+                       skip_romstage();
                }
        }
        /* Setup the console */
@@ -122,8 +115,7 @@ static void main(unsigned long bist)
 #endif
        disable_watchdogs();
 //     dump_ipmi_registers();
-//     mainboard_set_e7520_leds();     
-//     memreset_setup();
+//     mainboard_set_e7520_leds();
        sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
        dump_pci_devices();
@@ -133,7 +125,7 @@ static void main(unsigned long bist)
        //dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
 
-#if 0 // temporarily disabled 
+#if 0 // temporarily disabled
        /* Check the first 1M */
 //     ram_check(0x00000000, 0x000100000);
 //     ram_check(0x00000000, 0x000a0000);
@@ -144,10 +136,11 @@ static void main(unsigned long bist)
 #if 0
        ram_check(0x00000000, 0x02000000);
 #endif
-       
-#if 0  
+
+#if 0
        while(1) {
                hlt();
        }
 #endif
 }
+