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We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
[coreboot.git] / src / mainboard / supermicro / x6dhe_g2 / mptable.c
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 2b5995bc0e75b4950fe8407bf77678161ea1d9e5..50b6299b4fa7f201f80b9edd9feaf085d70fbbf1 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -1,13 +1,14 @@
 #include <console/console.h>
 #include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
 {
        static const char sig[4] = "PCMP";
-       static const char oem[8] = "LNXI    ";
+       static const char oem[8] = "COREBOOT";
        static const char productid[12] = "X6DHE       ";
        struct mp_config_table *mc;
        unsigned char bus_num;
@@ -35,7 +36,7 @@ void *smp_write_config_table(void *v)
        mc->reserved = 0;
 
        smp_write_processors(mc);
-       
+
        {
                device_t dev;
 
@@ -43,11 +44,9 @@ void *smp_write_config_table(void *v)
                dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
                if (dev) {
                        bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-               }
-               else {
+               } else {
                        printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
-
-                       bus_esb6300_2 = 6;
+                       bus_esb6300_1 = 6;
                }
                /* esb6300_1 */
                dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
@@ -55,37 +54,29 @@ void *smp_write_config_table(void *v)
                        bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                        bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                        bus_isa++;
-               }
-               else {
+               } else {
                        printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-
-                       bus_esb6300_1 = 7;
+                       bus_esb6300_2 = 7;
                        bus_isa = 8;
                }
                /* pxhd-1 */
                dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
                if (dev) {
                        bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-               }
-               else {
+               } else {
                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
-
                        bus_pxhd_1 = 2;
                }
                /* pxhd-2 */
                dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
                if (dev) {
                        bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-               }
-               else {
+               } else {
                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
                        bus_pxhd_2 = 3;
                }
        }
-       
+
        /* define bus and isa numbers */
        for(bus_num = 0; bus_num < bus_isa; bus_num++) {
                smp_write_bus(mc, bus_num, "PCI   ");
@@ -94,8 +85,8 @@ void *smp_write_config_table(void *v)
 
        /* IOAPIC handling */
 
-       smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
-       smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
+       smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+       smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
        {
                struct resource *res;
                device_t dev;
@@ -106,8 +97,7 @@ void *smp_write_config_table(void *v)
                        if (res) {
                                smp_write_ioapic(mc, 0x04, 0x20, res->base);
                        }
-               }
-               else {
+               } else {
                        printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
                        printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
                }
@@ -118,47 +108,21 @@ void *smp_write_config_table(void *v)
                        if (res) {
                                smp_write_ioapic(mc, 0x05, 0x20, res->base);
                        }
-               }
-               else {
+               } else {
                        printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
                        printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
                }
        }
 
-       
+       mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
+
        /* ISA backward compatibility interrupts  */
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x00, 0x02, 0x00);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x01, 0x02, 0x01);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x00, 0x02, 0x02);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x03, 0x02, 0x03);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x04, 0x02, 0x04);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
                0x00, 0x74, 0x02, 0x10);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x06, 0x02, 0x06);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, // added
-               bus_isa, 0x07, 0x02, 0x07);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x08, 0x02, 0x08);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x09, 0x02, 0x09);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
                0x00, 0x77, 0x02, 0x17);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
                0x00, 0x75, 0x02, 0x13);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x0c, 0x02, 0x0c);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x0d, 0x02, 0x0d);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x0e, 0x02, 0x0e);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x0f, 0x02, 0x0f);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
                0x00, 0x7c, 0x02, 0x12);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
@@ -175,14 +139,14 @@ void *smp_write_config_table(void *v)
                bus_esb6300_2, 0x04, 0x02, 0x10);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
                bus_esb6300_2, 0x08, 0x02, 0x14);
-       
+
        /* Standard local interrupt assignments */
        smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
                bus_isa, 0x00, MP_APIC_ALL, 0x00);
        smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
                bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
-#warning "FIXME verify I have the irqs handled for all of the risers"
+       /* FIXME verify I have the irqs handled for all of the risers */
 
        /* Compute the checksums */
        mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
my coreboot WIP stuff (asus m5a99x-evo board)