run uart_init() from console_init, just like the other console initialization functions.

[coreboot.git] / src / mainboard / supermicro / x6dhe_g / romstage.c

diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index a6dfe502a2f1666c8f3eb851330ba6e538ee5fd7..b6c6c1d443106d8ba73feb936cddd76de7ce8ab0 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -16,8 +16,7 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "x6dhe_g_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
@@ -35,6 +34,10 @@
        0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+static void mch_reset(void) {}
+static void mainboard_set_e7520_pll(unsigned bits) {}
+static void mainboard_set_e7520_leds(void) {}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -42,7 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
-#include "arch/i386/lib/stages.c"
+#include "arch/x86/lib/stages.c"
 
 static void main(unsigned long bist)
 {
@@ -63,7 +66,6 @@ static void main(unsigned long bist)
 
        w83627hf_set_clksel_48(DUMMY_DEV);
        w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
-       uart_init();
        console_init();
 
        /* Halt if there was a built in self test failure */