Winbond W83627HF: Use existing functions instead of open-coding.

[coreboot.git] / src / mainboard / supermicro / h8dmr_fam10 / romstage.c

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 61340cf2c654f57b9a44ed73b1c545e6c81168d3..966ae3b6948120889b9b9e30f00ee64c0ddbc107 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -19,20 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 1
 
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -41,14 +30,11 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-
 #include <console/console.h>
 #include <lib.h>
-
+#include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -57,23 +43,16 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -81,31 +60,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
-
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
@@ -129,46 +93,41 @@ static void sio_setup(void)
        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
        dword |= (1 << 16);
        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-
 }
 
-#include "spd_addr.h"
+static const u8 spd_addr[] = {
+       //first node
+       RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+       //second node
+       RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
+#endif
+};
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
                CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
-       u32 bsp_apicid = 0;
-       u32 val;
-       u32 wants_reset;
+       u32 bsp_apicid = 0, val, wants_reset;
        msr_t msr;
 
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
-
                sio_setup();
-
-               /* Setup the mcp55 */
-               mcp55_enable_rom();
        }
 
        post_code(0x30);
 
-       if (bist == 0) {
+       if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-       }
 
        post_code(0x32);
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-       pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
        uart_init();
        console_init();
@@ -221,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
                msr.hi, msr.lo);