Winbond W83627HF: Use existing functions instead of open-coding.

[coreboot.git] / src / mainboard / supermicro / h8dmr / romstage.c

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 573f69eb30ffe375d26ede20cf88d78fdbdc12e2..e7875956b27c5121c6a99a3e6c8a2e175b7badf3 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -51,15 +51,10 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -78,13 +73,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
 {
         uint32_t dword;
         uint8_t byte;
+
         enable_smbus();
 //     smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
        smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
@@ -105,40 +100,31 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
-                       // Node 0
-                       DIMM0, DIMM2, 0, 0,
-                       DIMM1, DIMM3, 0, 0,
-                       // Node 1
-                       DIMM4, DIMM6, 0, 0,
-                       DIMM5, DIMM7, 0, 0,
+               // Node 0
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
+               // Node 1
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
        };
 
         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
                + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 
         if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-
                sio_setup();
-
-               /* Setup the mcp55 */
-               mcp55_enable_rom();
         }
 
-        if (bist == 0) {
+        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-        }
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-        pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
         uart_init();
         console_init();
@@ -177,13 +163,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                 msr=rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
         }
-
         enable_fid_change();
-
         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
         init_fidvid_bsp(bsp_apicid);
-
         // show final fid and vid
         {
                 msr_t msr;