run uart_init() from console_init, just like the other console initialization functions.

[coreboot.git] / src / mainboard / supermicro / h8dmr / romstage.c

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index d41067a2d2a4e2e422846d84b04db52a484f14bf..38aef5ea4fbbe4e322fcdc21dc0c31954fad05db 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -36,21 +36,22 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/early_serial.c"
+#include "superio/winbond/w83627hf/early_init.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -60,19 +61,18 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -118,18 +118,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               mcp55_enable_rom();
         }
 
         if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-        pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
-        uart_init();
         console_init();
 
        /* Halt if there was a built in self test failure */