Winbond W83627HF: Use existing functions instead of open-coding.

[coreboot.git] / src / mainboard / supermicro / h8dme / romstage.c

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 4f32816ebb79764ecee12b6a2564fc39aa2c5654..ff7b24f40e3ef7461f6c326296ed5f2fb84d1f26 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -29,39 +29,28 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
 static inline void dump_smbus_registers(void)
 {
@@ -136,23 +125,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -202,30 +181,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
                + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
 
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-
                sio_setup();
-
-               /* Setup the mcp55 */
-               mcp55_enable_rom();
        }
 
-       if (bist == 0) {
+       if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-       }
 
-       pnp_enter_ext_func_mode(SERIAL_DEV);
-       pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       pnp_exit_ext_func_mode(SERIAL_DEV);
+       w83627hf_set_clksel_48(DUMMY_DEV);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
        uart_init();
        console_init();
@@ -262,7 +232,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        ht_setup_chains_x(sysinfo);     // it will init sblnk and sbbusn, nodes, sbdn
 
 #if CONFIG_SET_FIDVID
-
        {
                msr_t msr;
                msr = rdmsr(0xc0010042);
@@ -270,15 +239,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                print_debug_hex32(msr.hi);
                print_debug_hex32(msr.lo);
                print_debug("\n");
-
        }
-
        enable_fid_change();
-
        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
        init_fidvid_bsp(bsp_apicid);
-
        // show final fid and vid
        {
                msr_t msr;
@@ -287,7 +251,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                print_debug_hex32(msr.hi);
                print_debug_hex32(msr.lo);
                print_debug("\n");
-
        }
 #endif
 
@@ -315,6 +278,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
        post_cache_as_ram();    // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-