* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RAMINIT_SYSINFO 1
-
-#define K8_ALLOCATE_IO_RANGE 1
-
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-// used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
-
-// #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
-static int smbus_send_byte_one(unsigned device, unsigned char val)
-{
- return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
-static void dump_smbus_registers(void)
+static inline void dump_smbus_registers(void)
{
u32 device;
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
-/* We don't do any switching yet.
+#if 0
+/* We don't do any switching yet. */
#define SMBUS_SWITCH1 0x48
#define SMBUS_SWITCH2 0x49
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_SWITCH1, device);
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
-*/
- /* nothing to do */
+#endif
+}
+
+#if 0
+static int smbus_send_byte_one(unsigned device, unsigned char val)
+{
+ return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
}
-/*
static inline void change_i2c_mux(unsigned device)
{
#define SMBUS_SWITCH1 0x48
print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
dump_smbus_registers();
}
-*/
+#endif
static inline int spd_read_byte(unsigned device, unsigned address)
{
}
#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
-
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-#define MCP55_NUM 1
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
-#define MCP55_PCI_E_X_0 4
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
-
- u32 value;
uint32_t dword;
uint8_t byte;
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-
}
/* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
memory on each CPU must be an exact match.
*/
static const uint16_t spd_addr[] = {
- RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
- RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
- RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
- RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
- RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
- RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
- RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
-#endif
+ // Node 0
+ RC0 | DIMM0, RC0 | DIMM2,
+ RC0 | DIMM4, RC0 | DIMM6,
+ RC0 | DIMM1, RC0 | DIMM3,
+ RC0 | DIMM5, RC0 | DIMM7,
+ // Node 1
+ RC1 | DIMM0, RC1 | DIMM2,
+ RC1 | DIMM4, RC1 | DIMM6,
+ RC1 | DIMM1, RC1 | DIMM3,
+ RC1 | DIMM5, RC1 | DIMM7,
};
- struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
- mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
- pnp_enter_ext_func_mode(SERIAL_DEV);
- pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pnp_exit_ext_func_mode(SERIAL_DEV);
+ w83627hf_set_clksel_48(DUMMY_DEV);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-#if SET_FIDVID == 1
-
+#if CONFIG_SET_FIDVID
{
msr_t msr;
msr = rdmsr(0xc0010042);
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
#endif
-#if 1
+ init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
print_info("ht reset -\n");
soft_reset();
}
-#endif
+
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
enable_smbus(); /* enable in sio_setup */
- memreset_setup();
-
- //do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
-// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
projects / coreboot.git / blobdiff