Re-integrate "USE_OPTION_TABLE" code.

[coreboot.git] / src / mainboard / roda / rk886ex / romstage.c

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index c888871e5f4288c18cbb430a10b8fa353d9247c8..19b29053e38c0184d1723fe3035d441330c245ce 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -35,18 +35,15 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
 #define DBGP_DEFAULT 1
 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
+#include "pc80/usbdebug_serial.c"
 #endif
 
 #include "lib/ramtest.c"
@@ -184,7 +181,7 @@ static void rcba_config(void)
        RCBA32(0x3400) = (1 << 2);
 
        /* Disable unused devices */
-       RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | 
+       RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
                         FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
        RCBA32(0x3418) |= (1 << 0); // Required.
 
@@ -266,7 +263,7 @@ static void init_artec_dongle(void)
 #include <cbmem.h>
 
 // Now, this needs to be included because it relies on the symbol
-// __PRE_RAM__ being set during CAR stage (in order to compile the 
+// __PRE_RAM__ being set during CAR stage (in order to compile the
 // BSS free versions of the functions). Either rewrite the code
 // to be always BSS free, or invent a flag that's better suited than
 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
@@ -283,14 +280,18 @@ void main(unsigned long bist)
        }
 
        ich7_enable_lpc();
+
+       /* Force PCIRST# */
+       pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+
        early_superio_config();
 
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG_DIRECT
-       i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       i82801gx_enable_usbdebug(DBGP_DEFAULT);
+       early_usbdebug_init();
 #endif
 
        console_init();
@@ -299,8 +300,9 @@ void main(unsigned long bist)
        report_bist_failure(bist);
 
        if (MCHBAR16(SSKPD) == 0xCAFE) {
-               printk(BIOS_DEBUG, "soft reset detected.\n");
-               boot_mode = 1;
+               printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+               outb(0x6, 0xcf9);
+               while (1) asm("hlt");
        }
 
        /* Perform some early chipset initialization required
@@ -330,7 +332,7 @@ void main(unsigned long bist)
 
        /* Enable SPD ROMs and DDR-II DRAM */
        enable_smbus();
-       
+
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
        dump_spd_registers();
 #endif
@@ -340,8 +342,8 @@ void main(unsigned long bist)
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
 
-       /* This should probably go away. Until now it is required 
-        * and mainboard specific 
+       /* This should probably go away. Until now it is required
+        * and mainboard specific
         */
        rcba_config();
 
@@ -385,7 +387,7 @@ void main(unsigned long bist)
                 * memory completely, but that's a wonderful clean up task for another
                 * day.
                 */
-               if (resume_backup_memory) 
+               if (resume_backup_memory)
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */