Remove lib/ramtest.c-include from all CAR boards.

[coreboot.git] / src / mainboard / rca / rm4100 / romstage.c

diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index c93cec6b37fe47604ebf7b53dcca7a46606e2812..c838da1f1a73ac52b053a022767f573d0d94f71d 100644 (file)
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -25,10 +25,9 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
+#include <lib.h>
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
@@ -88,18 +87,16 @@ static void mb_early_setup(void)
        /* CPU Frequency Strap */
        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
        /* ACPI base address and enable Resource Indicator */
-       pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); 
+       pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
        /* Enable the SMBUS */
        enable_smbus();
        /* ACPI base address and disable Resource Indicator */
-       pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); 
+       pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
        /*  ACPI Enable */
        pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
 }
 
-#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
        if (bist == 0) {
                if (memory_initialized()) {