Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / pcengines / alix1c / romstage.c

diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 395e1778009e73d9aaa386396f7094aeba693613..ed9324ea447b8b0532af0a03a5fcee430447df2b 100644 (file)
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -36,9 +36,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
 
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -114,11 +112,6 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "cpu/amd/model_lx/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"
 
-/** Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-}
-
 void main(unsigned long bist)
 {
        static const struct mem_controller memctrl[] = {
@@ -137,7 +130,6 @@ void main(unsigned long bist)
         */
        cs5536_disable_internal_uart();
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       mb_gpio_init();
        uart_init();
        console_init();
 
@@ -150,10 +142,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory */
-       /* Enable this only if you are having questions. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Switch from Cache as RAM to real RAM.
         *
         * There are two ways we could think about this.
@@ -187,4 +175,3 @@ void main(unsigned long bist)
        void done_cache_as_ram_main(void);
        done_cache_as_ram_main();
 }
-