Re-integrate "USE_OPTION_TABLE" code.

[coreboot.git] / src / mainboard / msi / ms9652_fam10 / romstage.c

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 763a2b84bfb37f4965715b418319de01cdc6fb0f..4b7fe8f1c785e1721e71a72136d08c9c5c0c2580 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0
@@ -33,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
 
@@ -46,18 +43,10 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-
-static void post_code(u8 value) {
-       outb(value, 0x80);
-}
-
-#include "arch/i386/lib/console.c"
-#if CONFIG_USBDEBUG_DIRECT
-#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
-#include "pc80/usbdebug_direct_serial.c"
+#include <console/console.h>
+#if CONFIG_USBDEBUG
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
 #endif
 #include "lib/ramtest.c"
 
@@ -66,6 +55,8 @@ static void post_code(u8 value) {
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -75,7 +66,7 @@ static void post_code(u8 value) {
 
 #include "northbridge/amd/amdfam10/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
@@ -84,14 +75,6 @@ static void post_code(u8 value) {
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
        /* nothing to do */
@@ -103,10 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -130,22 +111,22 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void sio_setup(void)
 {
-       unsigned value;
-       uint32_t dword;
-       uint8_t byte;
+       u32 dword;
+       u8 byte;
 
        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
        byte |= 0x20;
@@ -157,8 +138,6 @@ static void sio_setup(void)
 }
 
 #include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -205,9 +184,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG_DIRECT
-       mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
-       early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+       mcp55_enable_usbdebug(DBGP_DEFAULT);
+       early_usbdebug_init();
 #endif
 
        val = cpuid_eax(1);
@@ -257,7 +236,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
@@ -279,6 +258,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        msr=rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
+       init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
        wants_reset = mcp55_early_setup_x();
 
@@ -301,9 +281,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        printk(BIOS_DEBUG, "enable_smbus()\n");
        enable_smbus();
-       post_code(0x3E);
 
-       memreset_setup();
        post_code(0x40);
 
        printk(BIOS_DEBUG, "raminit_amdmct()\n");