Drop console/console.c and pc80/serial.c from mainboards'

[coreboot.git] / src / mainboard / msi / ms7260 / romstage.c

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 9016075fb9338cfc1c965fab26ed3b2e9283a745..167fa34e265c7226f04d58dc3a8161ae4fad261b 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -33,10 +33,10 @@
 #endif
 
 /* Used by init_cpus and fidvid. */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -55,8 +55,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
@@ -75,7 +74,7 @@
 
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 /* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
@@ -83,7 +82,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void) {}
 static void memreset(int controllers, const struct mem_controller *ctrl) {}
 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
 
@@ -93,10 +91,11 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 }
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
+
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -115,7 +114,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -144,16 +143,17 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
+               // Node 0
                (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
                (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+               // Node 1
                (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
                (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
        };
 
-       struct sys_info *sysinfo =
-           (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+               + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
 
@@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
        print_debug("bsp_apicid=");
        print_debug_hex8(bsp_apicid);
-       print_debug("\r\n");
+       print_debug("\n");
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
        /* In BSP so could hold all AP until sysinfo is in RAM. */
@@ -214,13 +214,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* Set up chains and store link pair for optimization later. */
        ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
        {
                msr_t msr = rdmsr(0xc0010042);
                print_debug("begin msr fid, vid ");
                print_debug_hex32(msr.hi);
                print_debug_hex32(msr.lo);
-               print_debug("\r\n");
+               print_debug("\n");
        }
 
        enable_fid_change();
@@ -232,17 +232,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                print_debug("end   msr fid, vid ");
                print_debug_hex32(msr.hi);
                print_debug_hex32(msr.lo);
-               print_debug("\r\n");
+               print_debug("\n");
        }
 #endif
 
+       init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
        needs_reset |= optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        needs_reset |= mcp55_early_setup_x();
 
        /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
        if (needs_reset) {
-               print_info("ht reset -\r\n");
+               print_info("ht reset -\n");
                soft_reset();
        }
        allow_all_aps_stop(bsp_apicid);
@@ -252,11 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        enable_smbus();
 
-       memreset_setup();
-
-       /* Do we need apci timer, tsc...., only debug need it for better output */
        /* All AP stopped? */
-       // init_timer(); /* Need to use TMICT to synconize FID/VID. */
 
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);